From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2E1CC43461 for ; Thu, 17 Sep 2020 14:20:45 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1925F22227 for ; Thu, 17 Sep 2020 14:20:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Rvz4r3HF" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1925F22227 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Q6D0iVrH/TcbMzMZucSeyCxUsOdtUHb9CBsmL+pWxQo=; b=Rvz4r3HFGkFXlFaFQTEtA8EeX L+j9V3flOLuc+wFnXArQ6YLQw7dshzQGHaPBlwRG37BctXk+AY14F2D7LO18Xtv0nIPQg8WfnduRF Uc2b21ClGgpbfuxmXi2IIAxsOdbvmeiPZ5VxMChOpF6W8tVXsDO+nvs559hln24ODU1RnsxJ3VHHU OxMCGcz1ySswlJ0yjFGCs9+GUOea0Q2UNmyY9HC7D9EmOuD4SELufLy3m4r3TGu6C1o4jl7WLOzNw 5aA+H0NYuz/34CpTANqCVXdUhENFL7L3rNKB6tFb4oaeKAaSEAnJsufy1IFcpOlTFT4gsof0i54uB /1Dmkpf4g==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kIukt-0001rh-GR; Thu, 17 Sep 2020 14:19:23 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kIukp-0001qe-V3 for linux-arm-kernel@lists.infradead.org; Thu, 17 Sep 2020 14:19:21 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EBC1730E; Thu, 17 Sep 2020 07:19:15 -0700 (PDT) Received: from [192.168.1.190] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 95B3B3F718; Thu, 17 Sep 2020 07:19:13 -0700 (PDT) Subject: Re: [PATCH v2 22/37] arm64: mte: Add in-kernel MTE helpers To: Catalin Marinas , Andrey Konovalov References: <4ac1ed624dd1b0851d8cf2861b4f4aac4d2dbc83.1600204505.git.andreyknvl@google.com> <20200917134653.GB10662@gaia> From: Vincenzo Frascino Message-ID: <7904f7c2-cf3b-315f-8885-e8709c232718@arm.com> Date: Thu, 17 Sep 2020 15:21:41 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20200917134653.GB10662@gaia> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200917_101920_087712_990D95C0 X-CRM114-Status: GOOD ( 35.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org, Marco Elver , Elena Petrova , Kevin Brodsky , Will Deacon , Branislav Rankov , kasan-dev@googlegroups.com, linux-kernel@vger.kernel.org, linux-mm@kvack.org, Alexander Potapenko , Dmitry Vyukov , Andrey Ryabinin , Andrew Morton , Evgenii Stepanov Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 9/17/20 2:46 PM, Catalin Marinas wrote: > On Tue, Sep 15, 2020 at 11:16:04PM +0200, Andrey Konovalov wrote: >> diff --git a/arch/arm64/include/asm/mte-helpers.h b/arch/arm64/include/asm/mte-helpers.h >> new file mode 100644 >> index 000000000000..5dc2d443851b >> --- /dev/null >> +++ b/arch/arm64/include/asm/mte-helpers.h >> @@ -0,0 +1,48 @@ >> +/* SPDX-License-Identifier: GPL-2.0 */ >> +/* >> + * Copyright (C) 2020 ARM Ltd. >> + */ >> +#ifndef __ASM_MTE_ASM_H >> +#define __ASM_MTE_ASM_H >> + >> +#define __MTE_PREAMBLE ".arch armv8.5-a\n.arch_extension memtag\n" > > Because of how the .arch overrides a previous .arch, we should follow > the ARM64_ASM_PREAMBLE introduced in commit 1764c3edc668 ("arm64: use a > common .arch preamble for inline assembly"). The above should be > something like: > > #define __MTE_PREAMBLE ARM64_ASM_PREAMBLE ".arch_extension memtag" > > with the ARM64_ASM_PREAMBLE adjusted to armv8.5-a if available. Good idea, I was not aware of commit 1764c3edc668. I will fix it accordingly. > >> +#define MTE_GRANULE_SIZE UL(16) >> +#define MTE_GRANULE_MASK (~(MTE_GRANULE_SIZE - 1)) >> +#define MTE_TAG_SHIFT 56 >> +#define MTE_TAG_SIZE 4 >> +#define MTE_TAG_MASK GENMASK((MTE_TAG_SHIFT + (MTE_TAG_SIZE - 1)), MTE_TAG_SHIFT) >> +#define MTE_TAG_MAX (MTE_TAG_MASK >> MTE_TAG_SHIFT) > > In v1 I suggested we keep those definitions in mte-def.h (or > mte-hwdef.h) so that they can be included in cache.h. Anything else > should go in mte.h, I don't see the point of two headers for various MTE > function prototypes. > This is what I did in my patches I shared with Andrey. I suppose that since in this version he introduced some functions that are needed in this file, he reverted to the old name (mte-helper.h). >> + >> +#ifndef __ASSEMBLY__ >> + >> +#include >> + >> +#ifdef CONFIG_ARM64_MTE >> + >> +#define mte_get_ptr_tag(ptr) ((u8)(((u64)(ptr)) >> MTE_TAG_SHIFT)) > > I wonder whether this could also be an inline function that takes a void > *ptr. > >> diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c >> index 52a0638ed967..e238ffde2679 100644 >> --- a/arch/arm64/kernel/mte.c >> +++ b/arch/arm64/kernel/mte.c >> @@ -72,6 +74,52 @@ int memcmp_pages(struct page *page1, struct page *page2) >> return ret; >> } >> >> +u8 mte_get_mem_tag(void *addr) >> +{ >> + if (system_supports_mte()) >> + asm volatile(ALTERNATIVE("ldr %0, [%0]", >> + __MTE_PREAMBLE "ldg %0, [%0]", >> + ARM64_MTE) >> + : "+r" (addr)); > > This doesn't do what you think it does. LDG indeed reads the tag from > memory but LDR loads the actual data at that address. Instead of the > first LDR, you may want something like "mov %0, #0xf << 56" (and use > some macros to avoid the hard-coded 56). > The result of the load should never be used since it is meaningful only if system_supports_mte(). It should be only required for compilation purposes. Said that, I think I like more your solution hence I am going to adopt it. >> + >> + return 0xF0 | mte_get_ptr_tag(addr); >> +} >> + >> +u8 mte_get_random_tag(void) >> +{ >> + u8 tag = 0xF; >> + u64 addr = 0; >> + >> + if (system_supports_mte()) { >> + asm volatile(ALTERNATIVE("add %0, %0, %0", >> + __MTE_PREAMBLE "irg %0, %0", >> + ARM64_MTE) >> + : "+r" (addr)); > > What was the intention here? The first ADD doubles the pointer value and > gets a tag out of it (possibly doubled as well, depends on the carry > from bit 55). Better use something like "orr %0, %0, #0xf << 56". > Same as above but I will use the orr in the next version. >> + >> + tag = mte_get_ptr_tag(addr); >> + } >> + >> + return 0xF0 | tag; > > This function return seems inconsistent with the previous one. I'd > prefer the return line to be the same in both. > The reason why it is different is that in this function extracting the tag from the address makes sense only if irg is executed. I can initialize addr to 0xf << 56 and make them the same. >> +} >> + >> +void *mte_set_mem_tag_range(void *addr, size_t size, u8 tag) >> +{ >> + void *ptr = addr; >> + >> + if ((!system_supports_mte()) || (size == 0)) >> + return addr; >> + >> + /* Make sure that size is aligned. */ >> + WARN_ON(size & (MTE_GRANULE_SIZE - 1)); >> + >> + tag = 0xF0 | (tag & 0xF); > > No point in tag & 0xf, the top nibble doesn't matter as you or 0xf0 in. > Agree, will remove in the next version. >> + ptr = (void *)__tag_set(ptr, tag); >> + >> + mte_assign_mem_tag_range(ptr, size); >> + >> + return ptr; >> +} >> + >> static void update_sctlr_el1_tcf0(u64 tcf0) >> { >> /* ISB required for the kernel uaccess routines */ >> diff --git a/arch/arm64/lib/mte.S b/arch/arm64/lib/mte.S >> index 03ca6d8b8670..cc2c3a378c00 100644 >> --- a/arch/arm64/lib/mte.S >> +++ b/arch/arm64/lib/mte.S >> @@ -149,3 +149,20 @@ SYM_FUNC_START(mte_restore_page_tags) >> >> ret >> SYM_FUNC_END(mte_restore_page_tags) >> + >> +/* >> + * Assign allocation tags for a region of memory based on the pointer tag >> + * x0 - source pointer >> + * x1 - size >> + * >> + * Note: size must be non-zero and MTE_GRANULE_SIZE aligned >> + */ >> +SYM_FUNC_START(mte_assign_mem_tag_range) >> + /* if (src == NULL) return; */ >> + cbz x0, 2f >> +1: stg x0, [x0] >> + add x0, x0, #MTE_GRANULE_SIZE >> + sub x1, x1, #MTE_GRANULE_SIZE >> + cbnz x1, 1b >> +2: ret >> +SYM_FUNC_END(mte_assign_mem_tag_range) > > I thought Vincenzo agreed to my comments on the previous version w.r.t. > the fist cbz and the last cbnz: > > https://lore.kernel.org/linux-arm-kernel/921c4ed0-b5b5-bc01-5418-c52d80f1af59@arm.com/ > Ups, this is my fault, I just realized I missed to unstash this change. Will be present in the next version. -- Regards, Vincenzo _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel