From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28C0BC4338F for ; Thu, 12 Aug 2021 11:53:09 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7DFAB60F91 for ; Thu, 12 Aug 2021 11:53:06 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 7DFAB60F91 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:Cc:To:Subject:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=roXmX5e/hG/Bh1p2WDt0yWG7dt1Gh1HV4p5nqw0sW9Y=; b=kV1tCdwMJ6v+O2ch+ilmjFi6rQ iqvajYLfhdnIhva+381FZLvf6clplDMCvz+CB/hrDXmEuTvi+JS11g8n+vLU1XqFmndX8Y3fB9Tad 2BW9T3k9VSxVgb0fw38dEiyKt1kKr/QHiqrJ9fJPZ2s8jE2ay2BJh3vYx8AxFsznpvDplA0S/eenA kJFph5dfaKATPbAbc+xzpSZMumhGHaygQbwkmp2twAnXjtCTmylS98C2xuJaGxGQN76OEVay1kHN7 jQ6aNJMt4CDKVIyBC0rkcq50JAEDlR20GYwelP84fpjN229FmP/VAQTNT91yJrxS8lXmrzOetQfT2 9RRHz/Ig==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mE9EN-009sGE-3R; Thu, 12 Aug 2021 11:50:39 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mE9EJ-009sFU-Ab for linux-arm-kernel@lists.infradead.org; Thu, 12 Aug 2021 11:50:37 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A86F71042; Thu, 12 Aug 2021 04:50:27 -0700 (PDT) Received: from [192.168.0.110] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C16943F718; Thu, 12 Aug 2021 04:50:26 -0700 (PDT) Subject: Re: [PATCH] irqchip/gic-v3: Fix priority comparison when non-secure priorities are used To: Marc Zyngier , Chen-Yu Tsai Cc: Thomas Gleixner , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20210811171505.1502090-1-wenst@chromium.org> <87fsvfal4n.wl-maz@kernel.org> From: Alexandru Elisei Message-ID: <79eabae1-e4a3-7a12-7aa0-3680569584e5@arm.com> Date: Thu, 12 Aug 2021 12:51:34 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.12.0 MIME-Version: 1.0 In-Reply-To: <87fsvfal4n.wl-maz@kernel.org> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210812_045035_519874_2F86BC3F X-CRM114-Status: GOOD ( 28.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, After re-familiarizing myself with the spec, it starting to look to me like indeed there's something not quite right (read as: totally broken) with my patch. Arm IHI 0069F, the pseudocode for reading ICC_RPR_EL1 (page 11-797), says that the priority returned is unchanged if SCTLR_EL3.FIQ == 0. This means that the ICC_RPR_EL1 read will return the secure view (the value as it is stored by the GIC) of the priority, so for pseudo-nmis it will return (GICD_INT_NMI_PRI >> 1) | 0x80, which definitely != GICD_INT_NMI_PRI. This is further confirmed by this statement on page 4-67: "When GICD_CTLR.DS == 0, [..] For Non-secure access to ICC_PMR_EL1 and ICC_RPR_EL1 when SCR_EL3.FIQ == 0: The Secure, unshifted view applies." I don't know how I missed that during testing. Did a quick test on the model with PMU NMIs (GICD_CTRL.DS = 0, SCTLR_EL2.FIQ = 0), gic_handle_nmi() was not being called at all, but when I changed the comparison to gic_read_rpr() == ((GICD_INT_NMI_PRI >> 1) | 0x80), NMIs were being correctly handled again. Will try to run some more tests on real hardware and see if I can confirm this. Thanks, Alex On 8/11/21 7:31 PM, Marc Zyngier wrote: > + Alex, who introduced this. > > On Wed, 11 Aug 2021 18:15:05 +0100, > Chen-Yu Tsai wrote: >> When non-secure priorities are used, compared to the raw priority set, >> the value read back from RPR is also right-shifted by one and the >> highest bit set. >> >> Add a macro to do the modifications to the raw priority when doing the >> comparison against the RPR value. This corrects the pseudo-NMI behavior >> when non-secure priorities in the GIC are used. Tested on 5.10 with >> the "IPI as pseudo-NMI" series [1] applied on MT8195. >> >> [1] https://lore.kernel.org/linux-arm-kernel/1604317487-14543-1-git-send-email-sumit.garg@linaro.org/ >> >> Fixes: 336780590990 ("irqchip/gic-v3: Support pseudo-NMIs when SCR_EL3.FIQ == 0") >> Signed-off-by: Chen-Yu Tsai >> --- >> drivers/irqchip/irq-gic-v3.c | 11 ++++++++++- >> 1 file changed, 10 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c >> index e0f4debe64e1..e7a0b55413db 100644 >> --- a/drivers/irqchip/irq-gic-v3.c >> +++ b/drivers/irqchip/irq-gic-v3.c >> @@ -100,6 +100,15 @@ EXPORT_SYMBOL(gic_pmr_sync); >> DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities); >> EXPORT_SYMBOL(gic_nonsecure_priorities); >> >> +#define GICD_INT_RPR_PRI(priority) \ >> + ({ \ >> + u32 __priority = (priority); \ >> + if (static_branch_unlikely(&gic_nonsecure_priorities)) \ >> + __priority = 0x80 | (__priority >> 1); \ >> + \ >> + __priority; \ > This doesn't reflect what the pseudocode says of a read of ICC_RPR_EL1 > AFAICS. When the priority is activated, it is indeed shifted. But a > read of RPR does appear to shift things back (and you loose the lowest > bit in the process). Please see 'aarch64/support/ICC_RPR_EL1' in the > architecture spec. > > Can you confirm that SCR_EL3.FIQ is set on your system? > > Thanks, > > M. > >> + }) >> + >> /* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */ >> static refcount_t *ppi_nmi_refs; >> >> @@ -687,7 +696,7 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs >> return; >> >> if (gic_supports_nmi() && >> - unlikely(gic_read_rpr() == GICD_INT_NMI_PRI)) { >> + unlikely(gic_read_rpr() == GICD_INT_RPR_PRI(GICD_INT_NMI_PRI))) { >> gic_handle_nmi(irqnr, regs); >> return; >> } > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel