From: Hugh Cole-Baker <sigmaris@gmail.com>
To: Robin Murphy <robin.murphy@arm.com>
Cc: heiko@sntech.de, hjc@rock-chips.com,
dri-devel@lists.freedesktop.org,
linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org, ezequiel@collabora.com
Subject: Re: [PATCH v2 3/3] arm64: dts: rockchip: enable gamma control on RK3399
Date: Thu, 15 Sep 2022 17:53:07 +0100 [thread overview]
Message-ID: <7B966E6B-1D3F-4975-AC44-1840951257F1@gmail.com> (raw)
In-Reply-To: <9196035b-273a-adca-2b87-c70bbab7f5c9@arm.com>
> On 15 Sep 2022, at 15:40, Robin Murphy <robin.murphy@arm.com> wrote:
>
> On 2021-10-19 22:58, Hugh Cole-Baker wrote:
>> Define the memory region on RK3399 VOPs containing the gamma LUT at
>> base+0x2000.
>> Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
>> ---
>> Changes from v1: no changes in this patch
>> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>> diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> index 3871c7fd83b0..9cbf6ccdd256 100644
>> --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
>> @@ -1619,7 +1619,7 @@ i2s2: i2s@ff8a0000 {
>> vopl: vop@ff8f0000 {
>> compatible = "rockchip,rk3399-vop-lit";
>> - reg = <0x0 0xff8f0000 0x0 0x3efc>;
>> + reg = <0x0 0xff8f0000 0x0 0x2000>, <0x0 0xff8f2000 0x0 0x400>;
>> interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
>> assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
>> assigned-clock-rates = <400000000>, <100000000>;
>> @@ -1676,7 +1676,7 @@ vopl_mmu: iommu@ff8f3f00 {
>> vopb: vop@ff900000 {
>> compatible = "rockchip,rk3399-vop-big";
>> - reg = <0x0 0xff900000 0x0 0x3efc>;
>> + reg = <0x0 0xff900000 0x0 0x2000>, <0x0 0xff902000 0x0 0x1000>;
>
> Doesn't the second range still need to be shorter than 0xf00 to avoid overlapping the IOMMU?
>
> Robin.
This should be OK, the other registers are in the range ff900000-ff902000, the
gamma LUT occupies the range ff902000-ff903000, and then the IOMMU registers
begin at ff903f00. I don't see any overlaps with the IOMMU unless I'm
misreading the dts.
>> interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
>> assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
>> assigned-clock-rates = <400000000>, <100000000>;
br, Hugh.
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next prev parent reply other threads:[~2022-09-15 16:54 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-19 21:58 [PATCH v2 0/3] drm/rockchip: support gamma control on RK3399 Hugh Cole-Baker
2021-10-19 21:58 ` [PATCH v2 1/3] drm/rockchip: define gamma registers for RK3399 Hugh Cole-Baker
2022-08-07 12:38 ` Milan P. Stanić
2022-09-13 12:58 ` Linus Heckemann
2021-10-19 21:58 ` [PATCH v2 2/3] drm/rockchip: support gamma control on RK3399 Hugh Cole-Baker
2021-10-19 21:58 ` [PATCH v2 3/3] arm64: dts: rockchip: enable " Hugh Cole-Baker
2022-09-15 14:40 ` Robin Murphy
2022-09-15 16:53 ` Hugh Cole-Baker [this message]
2022-09-15 17:11 ` Robin Murphy
2022-09-15 13:40 ` (subset) [PATCH v2 0/3] drm/rockchip: support " Heiko Stuebner
2022-09-15 13:49 ` Heiko Stuebner
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