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* [PATCH v12 0/3] media: mediatek: support mdp3 on mt8183 platform
@ 2022-03-17 14:56 Moudy Ho
  2022-03-17 14:56 ` [PATCH v12 1/3] dt-binding: mt8183: add Mediatek MDP3 dt-bindings Moudy Ho
  2022-03-17 14:56 ` [PATCH v12 2/3] dts: arm64: mt8183: add Mediatek MDP3 nodes Moudy Ho
  0 siblings, 2 replies; 8+ messages in thread
From: Moudy Ho @ 2022-03-17 14:56 UTC (permalink / raw)
  To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
	Hans Verkuil, Jernej Skrabec
  Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
	linux-media, devicetree, linux-arm-kernel, linux-mediatek,
	linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
	AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
	Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
	moudy.ho, jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
	Project_Global_Chrome_Upstream_Group

Change since v11:
- Rebase on linux-next tag:next-20220316
- Depend on:
  [1] https://patchwork.kernel.org/project/linux-mediatek/list/?series=624281
- Remove redundant hardware index in data-binding suggested by Rob Herring.
- Referring to Rob Herring's suggestion to improve some descriptions in the RDMA dt-binding
- Move MDP3 file folder from "./drive/media/platform/mtk-mdp3" to "./driver/media/platform/mediatek/mdp3"
- Fixed the V4L2 and MDP color format mapping error in RGB565 which checked by Benjamin Gaignard

Change since v10:
- The routing table needs to be discarded, and the calculation result
  on the SCP side is used to write a suitable mux setting for
  1 input port and 2 output ports.
- Adjust dts parsing flow to remove redundant HW IDs.
- Fix memory leak caused by no free path information in function "mdp_cmdq_send".

Change since v9:
- Keep only the MDP3 driver patches and split the remaining mmsys and
  mutex patches into another mail.
- Move mutex mod settings to corresponding driver and make relevant adjustments
  for this in MDP3 driver.
- Fix compile warning reported by kernel test robot.

Change since v8:
- Rebase on v5.16-rc2.
- Refer to Angelo's suggestion, adjust the register writing format to increase
  readability and significance.
- Refer to Angelo's suggestion, adjust or reduce inappropriate debugging
  messages.
- Refer to Rob Herring's suggestion to correct the the binding file
  to make it with the specification.
- Fix compile warning reported by kernel test robot.

Change since v7:
- Rebase on v5.15-rc6.
- Revise several V4L2 M2M settings to pass v4l2-compliance test.
- Integrate those same component dt-binding documents of DRM and MDP, and
  move them under the MMSYS domain.
- Split MMSYS and MUTEX into two different files according to
  their functional properties.

Changes since v6:
- Refactor GCE event to corresponding node.
- Fix dt_binding_check fail.
- Fix compilation errors.

Changes since v5:
- Rebase on v5.14-rc6.
- Move MMSYS/Mutex settings to corresponding driver.
- Revise the software license description and copyright.
- Remove unnecessary enum. or definitions.
- Optimize platform/chip definition conditions.
- Use general printing functions instead of MDP3 private ones.
- Fix compile warning.

Changes since v4:
- Rebase on v5.13-rc1.
- Remove the CMDQ flush flow to match the CMDQ API change.
- Integrate four of MDP's direct-link subcomponents into MDP controller node
  from syscon node to avoid illegal clock usage.
- Rewrite dt-binding in a JSON compatible subset of YAML
- Fix a bit of macro argument precedence.

Changes since v3:
- Rebase on v5.9-rc1.
- modify code for review comment from Rob Herring, cancel multiple nodes using
  same register base situation.
- control IOMMU port through pm runtime get/put to DMA components' device.
- SCP(VPU) driver revision.
- stop queuing jobs(remove flush_workqueue()) after mdp_m2m_release().
- add computation of plane address with data_offset.
- fix scale ratio check issue.
- add default v4l2_format setting.

Changes since v2:
- modify code for review comment from Tomasz Figa & Alexandre Courbot
- review comment from Rob Herring will offer code revision in v4, due to
  it's related to device node modification, will need to modify code
  architecture

Changes since v1:
- modify code for CMDQ v3 API support
- EC ipi cmd migration
- fix compliance test fail item (m2m cmd with -f) due to there is two problem in runing all format(-f) cmd:
1. out of memory before test complete
        Due to capture buffer mmap (refcount + 1) after reqbuf but seems
        no corresponding munmap called before device close.
        There are total 12XX items(formats) in format test and each format
        alloc 8 capture/output buffers.
2. unceasingly captureBufs() (randomly)
        Seems the break statement didn't catch the count == 0 situation:
        In v4l2-test-buffers.cpp, function: captureBufs()
                        ...
                        count--;
                        if (!node->is_m2m && !count)
                                break;
        Log is as attachment

I will paste the test result with problem part in another e-mail

Hi,

This is the first version of RFC patch for Media Data Path 3 (MDP3),
MDP3 is used for scaling and color format conversion.
support using GCE to write register in critical time limitation.
support V4L2 m2m device control.

Moudy Ho (3):
  dt-binding: mt8183: add Mediatek MDP3 dt-bindings
  dts: arm64: mt8183: add Mediatek MDP3 nodes
  media: platform: mtk-mdp3: add Mediatek MDP3 driver

 .../bindings/media/mediatek,mdp3-rdma.yaml    |  214 ++++
 .../bindings/media/mediatek,mdp3-rsz.yaml     |   54 +
 .../bindings/media/mediatek,mdp3-wrot.yaml    |   57 +
 .../bindings/soc/mediatek/mediatek,ccorr.yaml |   47 +
 .../bindings/soc/mediatek/mediatek,wdma.yaml  |   58 +
 arch/arm64/boot/dts/mediatek/mt8183.dtsi      |  108 +-
 drivers/media/platform/mediatek/Kconfig       |    1 +
 drivers/media/platform/mediatek/Makefile      |    1 +
 drivers/media/platform/mediatek/mdp3/Kconfig  |   20 +
 drivers/media/platform/mediatek/mdp3/Makefile |    6 +
 .../platform/mediatek/mdp3/mdp_reg_ccorr.h    |   19 +
 .../platform/mediatek/mdp3/mdp_reg_rdma.h     |   65 ++
 .../platform/mediatek/mdp3/mdp_reg_rsz.h      |   39 +
 .../platform/mediatek/mdp3/mdp_reg_wdma.h     |   47 +
 .../platform/mediatek/mdp3/mdp_reg_wrot.h     |   55 +
 .../platform/mediatek/mdp3/mtk-img-ipi.h      |  286 +++++
 .../platform/mediatek/mdp3/mtk-mdp3-cmdq.c    |  494 ++++++++
 .../platform/mediatek/mdp3/mtk-mdp3-cmdq.h    |   51 +
 .../platform/mediatek/mdp3/mtk-mdp3-comp.c    | 1023 +++++++++++++++++
 .../platform/mediatek/mdp3/mtk-mdp3-comp.h    |  185 +++
 .../platform/mediatek/mdp3/mtk-mdp3-core.c    |  350 ++++++
 .../platform/mediatek/mdp3/mtk-mdp3-core.h    |   86 ++
 .../platform/mediatek/mdp3/mtk-mdp3-m2m.c     |  789 +++++++++++++
 .../platform/mediatek/mdp3/mtk-mdp3-m2m.h     |   49 +
 .../platform/mediatek/mdp3/mtk-mdp3-regs.c    |  737 ++++++++++++
 .../platform/mediatek/mdp3/mtk-mdp3-regs.h    |  372 ++++++
 .../platform/mediatek/mdp3/mtk-mdp3-vpu.c     |  312 +++++
 .../platform/mediatek/mdp3/mtk-mdp3-vpu.h     |   78 ++
 28 files changed, 5602 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
 create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
 create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
 create mode 100644 drivers/media/platform/mediatek/mdp3/Kconfig
 create mode 100644 drivers/media/platform/mediatek/mdp3/Makefile
 create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_ccorr.h
 create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_rdma.h
 create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_rsz.h
 create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_wdma.h
 create mode 100644 drivers/media/platform/mediatek/mdp3/mdp_reg_wrot.h
 create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-img-ipi.h
 create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.c
 create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-cmdq.h
 create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.c
 create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-comp.h
 create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.c
 create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-core.h
 create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.c
 create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-m2m.h
 create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.c
 create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-regs.h
 create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.c
 create mode 100644 drivers/media/platform/mediatek/mdp3/mtk-mdp3-vpu.h

-- 
2.18.0


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* [PATCH v12 1/3] dt-binding: mt8183: add Mediatek MDP3 dt-bindings
  2022-03-17 14:56 [PATCH v12 0/3] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
@ 2022-03-17 14:56 ` Moudy Ho
  2022-03-30  8:17   ` moudy.ho
  2022-03-31 21:19   ` Rob Herring
  2022-03-17 14:56 ` [PATCH v12 2/3] dts: arm64: mt8183: add Mediatek MDP3 nodes Moudy Ho
  1 sibling, 2 replies; 8+ messages in thread
From: Moudy Ho @ 2022-03-17 14:56 UTC (permalink / raw)
  To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
	Hans Verkuil, Jernej Skrabec
  Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
	linux-media, devicetree, linux-arm-kernel, linux-mediatek,
	linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
	AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
	Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
	moudy.ho, jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
	Project_Global_Chrome_Upstream_Group

This patch adds DT binding documents for Media Data Path 3 (MDP3)
a unit in multimedia system combined with several components and
used for scaling and color format convert.

It can create multiple paths with different functions by assigning
different components, a simple diagram is as follows:

  +------------+          +------------+
  |    RDMA    |          |   ISP[*1]  |
  +---+--+--+--+          +-----+--+---+
      A  B  C                   2  1
      v  v  v                   v  v
      |  |  |                   |  |
      |  |  +---------+         |  |
      |  |            |         |  |
      |  +-------+    |         |  |
      |          |    |         |  |
      |  +-------+----+---------+  |
      |  |       |    |            |
      |  |       |    +---------+  |
      v  v       |              |  |
      A  2       |              |  |
    ********     |              |  |
  **        **   |              |  |
 *   PQ[*2]   *  |              |  |
  **        **   |              |  |
    ********     |              |  |
      |  |       |              |  |
      v  v       |              v  v
      A  2       |              C  1
  +---+--+---+   |        +-----+--+--+
  |    RSZ   |   |        |    RSZ    |
  +---+------+   |        +-----+--+--+
      D          |              3  4
      v          |              v  v
      |          |              |  |
      |  +-------+              |  |
      |  |                      |  |
      |  |  +-------------------+  |
      |  |  |                      |
      v  v  v                      v
      D  B  3                      4
  +---+--+--+--+         +---------+--+
  |    WROT    |         |    WDMA    |
  +------------+         +------------+

[*1] Direct-link path for camera input
[*2] A series of picture quality adjustment
     engines, composed of AAL, CCORR, TDSHP
     and COLOR

Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
 .../bindings/media/mediatek,mdp3-rdma.yaml    | 214 ++++++++++++++++++
 .../bindings/media/mediatek,mdp3-rsz.yaml     |  54 +++++
 .../bindings/media/mediatek,mdp3-wrot.yaml    |  57 +++++
 .../bindings/soc/mediatek/mediatek,ccorr.yaml |  47 ++++
 .../bindings/soc/mediatek/mediatek,wdma.yaml  |  58 +++++
 5 files changed, 430 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
 create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
 create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml

diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
new file mode 100644
index 000000000000..3bf59c3f521f
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
@@ -0,0 +1,214 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Read Direct Memory Access
+
+maintainers:
+  - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+  Mediatek Read Direct Memory Access(RDMA) component used to do read DMA.
+  It contains one line buffer to store the sufficient pixel data, and
+  must be siblings to the central MMSYS_CONFIG node.
+  For a description of the MMSYS_CONFIG binding, see
+  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+  for details.
+  The 1st RDMA is also used to be a controller node in Media Data Path 3(MDP3)
+  that containing MMSYS, MUTEX, GCE and SCP settings.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          # MDP3 controller node
+          - const: mediatek,mt8183-mdp3
+          - const: mediatek,mt8183-mdp3-rdma
+      - items:
+          # normal RDMA conponent
+          - const: mediatek,mt8183-mdp3-rdma
+
+  mediatek,scp:
+    description: |
+      The node of system control processor (SCP), using
+      the remoteproc & rpmsg framework.
+    $ref: '/schemas/types.yaml#/definitions/phandle'
+    maxItems: 1
+
+  mediatek,mdp3-comps:
+    description: |
+      MDP subsystem which has direct-link from Image Signal Processor(ISP).
+      When using the camera, the DMA of ISP PASS (DIP) module will directly
+      trigger MDP3 without other control (such as V4L2 M2M) to create
+      corresponding HW path.
+      The MDP3 controller must set up a series of registers at the beginning of
+      path creation which covering MMSYS, IMGSYS, and MDP3's components,
+      so that data flow can pass through MDP3.
+      The entire path is briefly described as follows
+      ISP --+
+            |
+            +-> DIP --+
+      ................|..............................................
+      (MDP3)          +->IMGI -+-> DL1 ->  RSZ -+-> PATH1 -> WROT
+                               |            ^   |
+                               |            |   |
+                               +-> DL2 -----+   +-> PATH2 -> WDMA
+                               |
+                               +---------------------------> EXTO
+    $ref: '/schemas/types.yaml#/definitions/string-array'
+    items:
+      enum:
+        # MDP direct-link input path selection, create a
+        # component for path connectedness of HW pipe control
+        - mediatek,mt8183-mdp3-dl1
+        - mediatek,mt8183-mdp3-dl2
+        # MDP direct-link output path selection, create a
+        # component for path connectedness of HW pipe control
+        - mediatek,mt8183-mdp3-path1
+        - mediatek,mt8183-mdp3-path2
+        # Input DMA of ISP PASS2 (DIP) module for raw image input
+        - mediatek,mt8183-mdp3-imgi
+        # Output DMA of ISP PASS2 (DIP) module for YUV image output
+        - mediatek,mt8183-mdp3-exto
+
+  reg:
+    items:
+      - description: basic RDMA HW address
+      - description: MDP direct-link 1st and 2nd input
+      - description: MDP direct-link 1st output
+      - description: MDP direct-link 2nd output
+      - description: ISP input and output
+
+  mediatek,gce-client-reg:
+    $ref: '/schemas/types.yaml#/definitions/phandle-array'
+    minItems: 1
+    items:
+      - description: GCE client for RDMA
+      - description: GCE client for dl1 and dl2
+      - description: GCE client for path1
+      - description: GCE client for path2
+      - description: GCE client for imgi and exto
+    description: |
+      The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+
+  power-domains:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: RDMA clock
+      - description: RSZ clock
+      - description: direck-link TX clock in MDP side
+      - description: direck-link RX clock in MDP side
+      - description: direck-link TX clock in ISP side
+      - description: direck-link RX clock in ISP side
+
+  iommus:
+    maxItems: 1
+
+  mediatek,mmsys:
+    description: The node of mux(multiplexer) controller for HW connections.
+    $ref: '/schemas/types.yaml#/definitions/phandle'
+
+  mediatek,mm-mutex:
+    description: |
+      Mediatek mutex, namely MUTEX, is used to send the triggers signals called
+      Start Of Frame(SOF) / End Of Frame(EOF) to each sub-modules on the data path.
+      In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
+      the shadow register.
+    $ref: '/schemas/types.yaml#/definitions/phandle'
+
+  mediatek,mailbox-gce:
+    description: |
+      The node of global command engine (GCE), used to read/write
+      registers with critical time limitation.
+    $ref: '/schemas/types.yaml#/definitions/phandle'
+
+  mboxes:
+    items:
+      - description: used for 1st data pipe from RDMA
+      - description: used for 2nd data pipe from RDMA
+      - description: used for 3rd data pipe from Direct-Link
+      - description: used for 4th data pipe from Direct-Link
+
+  gce-subsys:
+    description: |
+      sub-system id corresponding to the global command engine (GCE)
+      register address.
+    $ref: '/schemas/types.yaml#/definitions/phandle-array'
+
+if:
+  properties:
+    compatible:
+      contains:
+        const: mediatek,mt8183-mdp3
+
+then:
+  required:
+    - mediatek,scp
+    - mediatek,mmsys
+    - mediatek,mm-mutex
+    - mediatek,mailbox-gce
+    - mboxes
+    - gce-subsys
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - mediatek,gce-client-reg
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/mt8183-clk.h>
+    #include <dt-bindings/gce/mt8183-gce.h>
+    #include <dt-bindings/power/mt8183-power.h>
+    #include <dt-bindings/memory/mt8183-larb-port.h>
+
+    mdp3_rdma0: mdp3_rdma0@14001000 {
+      compatible = "mediatek,mt8183-mdp3",
+                   "mediatek,mt8183-mdp3-rdma";
+      mediatek,scp = <&scp>;
+      mediatek,mdp3-comps = "mediatek,mt8183-mdp3-dl1",
+                            "mediatek,mt8183-mdp3-dl2",
+                            "mediatek,mt8183-mdp3-path1",
+                            "mediatek,mt8183-mdp3-path2",
+                            "mediatek,mt8183-mdp3-imgi",
+                            "mediatek,mt8183-mdp3-exto";
+      reg = <0x14001000 0x1000>,
+            <0x14000000 0x1000>,
+            <0x14005000 0x1000>,
+            <0x14006000 0x1000>,
+            <0x15020000 0x1000>;
+      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>,
+                                <&gce SUBSYS_1400XXXX 0 0x1000>,
+                                <&gce SUBSYS_1400XXXX 0x5000 0x1000>,
+                                <&gce SUBSYS_1400XXXX 0x6000 0x1000>,
+                                <&gce SUBSYS_1502XXXX 0 0x1000>;
+      power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+      clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+               <&mmsys CLK_MM_MDP_RSZ1>,
+               <&mmsys CLK_MM_MDP_DL_TXCK>,
+               <&mmsys CLK_MM_MDP_DL_RX>,
+               <&mmsys CLK_MM_IPU_DL_TXCK>,
+               <&mmsys CLK_MM_IPU_DL_RX>;
+      iommus = <&iommu>;
+      mediatek,mmsys = <&mmsys>;
+      mediatek,mm-mutex = <&mutex>;
+      mediatek,mailbox-gce = <&gce>;
+      mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
+               <&gce 21 CMDQ_THR_PRIO_LOWEST>,
+               <&gce 22 CMDQ_THR_PRIO_LOWEST>,
+               <&gce 23 CMDQ_THR_PRIO_LOWEST>;
+      gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
+                   <&gce 0x14010000 SUBSYS_1401XXXX>,
+                   <&gce 0x14020000 SUBSYS_1402XXXX>,
+                   <&gce 0x15020000 SUBSYS_1502XXXX>;
+    };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
new file mode 100644
index 000000000000..0dcb1a883a8e
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Resizer
+
+maintainers:
+  - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+  One of Media Data Path 3 (MDP3) components used to do frame resizing.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt8183-mdp3-rsz
+
+  reg:
+    maxItems: 1
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/mt8183-clk.h>
+    #include <dt-bindings/gce/mt8183-gce.h>
+
+    mdp3_rsz0: mdp3_rsz0@14003000 {
+      compatible = "mediatek,mt8183-mdp3-rsz";
+      reg = <0x14003000 0x1000>;
+      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
+      clocks = <&mmsys CLK_MM_MDP_RSZ0>;
+    };
+
+    mdp3_rsz1: mdp3_rsz1@14004000 {
+      compatible = "mediatek,mt8183-mdp3-rsz";
+      reg = <0x14004000 0x1000>;
+      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
+      clocks = <&mmsys CLK_MM_MDP_RSZ1>;
+    };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
new file mode 100644
index 000000000000..f2c38a9b187d
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Write DMA with Rotation
+
+maintainers:
+  - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+  One of Media Data Path 3 (MDP3) components used to write DMA with frame rotation.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt8183-mdp3-wrot
+
+  reg:
+    maxItems: 1
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+
+  iommus:
+    maxItems: 1
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/mt8183-clk.h>
+    #include <dt-bindings/gce/mt8183-gce.h>
+    #include <dt-bindings/power/mt8183-power.h>
+    #include <dt-bindings/memory/mt8183-larb-port.h>
+
+    mdp3_wrot0: mdp3_wrot0@14005000 {
+      compatible = "mediatek,mt8183-mdp3-wrot";
+      reg = <0x14005000 0x1000>;
+      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+      power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+      clocks = <&mmsys CLK_MM_MDP_WROT0>;
+      iommus = <&iommu>;
+    };
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
new file mode 100644
index 000000000000..cf23f4f5bd69
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/mediatek/mediatek,ccorr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek color correction
+
+maintainers:
+  - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+  Mediatek color correction with 3X3 matrix.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt8183-mdp3-ccorr
+
+  reg:
+    maxItems: 1
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/mt8183-clk.h>
+    #include <dt-bindings/gce/mt8183-gce.h>
+
+    mdp3_ccorr: mdp3_ccorr@1401c000 {
+      compatible = "mediatek,mt8183-mdp3-ccorr";
+      reg = <0x1401c000 0x1000>;
+      mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
+      clocks = <&mmsys CLK_MM_MDP_CCORR>;
+    };
diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
new file mode 100644
index 000000000000..4057b5232e45
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/mediatek/mediatek,wdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Write Direct Memory Access
+
+maintainers:
+  - Matthias Brugger <matthias.bgg@gmail.com>
+
+description: |
+  Mediatek Write Direct Memory Access(WDMA) component used to write
+  the data into DMA.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - mediatek,mt8183-mdp3-wdma
+
+  reg:
+    maxItems: 1
+
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured by gce with
+      4 arguments defined in this property, such as phandle of gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  clocks:
+    minItems: 1
+
+  iommus:
+    maxItems: 1
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/mt8183-clk.h>
+    #include <dt-bindings/gce/mt8183-gce.h>
+    #include <dt-bindings/power/mt8183-power.h>
+    #include <dt-bindings/memory/mt8183-larb-port.h>
+
+    mdp3_wdma: mdp3_wdma@14006000 {
+      compatible = "mediatek,mt8183-mdp3-wdma";
+      reg = <0x14006000 0x1000>;
+      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+      power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+      clocks = <&mmsys CLK_MM_MDP_WDMA0>;
+      iommus = <&iommu>;
+    };
-- 
2.18.0


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^ permalink raw reply related	[flat|nested] 8+ messages in thread

* [PATCH v12 2/3] dts: arm64: mt8183: add Mediatek MDP3 nodes
  2022-03-17 14:56 [PATCH v12 0/3] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
  2022-03-17 14:56 ` [PATCH v12 1/3] dt-binding: mt8183: add Mediatek MDP3 dt-bindings Moudy Ho
@ 2022-03-17 14:56 ` Moudy Ho
  2022-03-17 15:26   ` AngeloGioacchino Del Regno
  1 sibling, 1 reply; 8+ messages in thread
From: Moudy Ho @ 2022-03-17 14:56 UTC (permalink / raw)
  To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
	Hans Verkuil, Jernej Skrabec
  Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
	linux-media, devicetree, linux-arm-kernel, linux-mediatek,
	linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
	AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
	Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
	moudy.ho, jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
	Project_Global_Chrome_Upstream_Group

Add device nodes for Media Data Path 3 (MDP3) modules.

Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8183.dtsi | 108 ++++++++++++++++++++++-
 1 file changed, 107 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index fc6ac2a46324..eaa6dac7768b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1389,6 +1389,79 @@
 			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
 		};
 
+		mdp3_rdma0: mdp3_rdma0@14001000 {
+			compatible = "mediatek,mt8183-mdp3",
+				     "mediatek,mt8183-mdp3-rdma";
+			mediatek,scp = <&scp>;
+			mediatek,mdp3-comps = "mediatek,mt8183-mdp3-dl1",
+					      "mediatek,mt8183-mdp3-dl2",
+					      "mediatek,mt8183-mdp3-path1",
+					      "mediatek,mt8183-mdp3-path2",
+					      "mediatek,mt8183-mdp3-imgi",
+					      "mediatek,mt8183-mdp3-exto";
+			reg = <0 0x14001000 0 0x1000>,
+			      <0 0x14000000 0 0x1000>,
+			      <0 0x14005000 0 0x1000>,
+			      <0 0x14006000 0 0x1000>,
+			      <0 0x15020000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>,
+						  <&gce SUBSYS_1400XXXX 0 0x1000>,
+						  <&gce SUBSYS_1400XXXX 0x5000 0x1000>,
+						  <&gce SUBSYS_1400XXXX 0x6000 0x1000>,
+						  <&gce SUBSYS_1502XXXX 0 0x1000>;
+			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+				 <&mmsys CLK_MM_MDP_RSZ1>,
+				 <&mmsys CLK_MM_MDP_DL_TXCK>,
+				 <&mmsys CLK_MM_MDP_DL_RX>,
+				 <&mmsys CLK_MM_IPU_DL_TXCK>,
+				 <&mmsys CLK_MM_IPU_DL_RX>;
+			iommus = <&iommu M4U_PORT_MDP_RDMA0>;
+			mediatek,mmsys = <&mmsys>;
+			mediatek,mm-mutex = <&mutex>;
+			mediatek,mailbox-gce = <&gce>;
+			mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
+				 <&gce 21 CMDQ_THR_PRIO_LOWEST>,
+				 <&gce 22 CMDQ_THR_PRIO_LOWEST>,
+				 <&gce 23 CMDQ_THR_PRIO_LOWEST>;
+			gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
+				     <&gce 0x14010000 SUBSYS_1401XXXX>,
+				     <&gce 0x14020000 SUBSYS_1402XXXX>,
+				     <&gce 0x15020000 SUBSYS_1502XXXX>;
+		};
+
+		mdp3_rsz0: mdp3_rsz0@14003000 {
+			compatible = "mediatek,mt8183-mdp3-rsz";
+			reg = <0 0x14003000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
+			clocks = <&mmsys CLK_MM_MDP_RSZ0>;
+		};
+
+		mdp3_rsz1: mdp3_rsz1@14004000 {
+			compatible = "mediatek,mt8183-mdp3-rsz";
+			reg = <0 0x14004000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
+			clocks = <&mmsys CLK_MM_MDP_RSZ1>;
+		};
+
+		mdp3_wrot0: mdp3_wrot0@14005000 {
+			compatible = "mediatek,mt8183-mdp3-wrot";
+			reg = <0 0x14005000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_MDP_WROT0>;
+			iommus = <&iommu M4U_PORT_MDP_WROT0>;
+		};
+
+		mdp3_wdma: mdp3_wdma@14006000 {
+			compatible = "mediatek,mt8183-mdp3-wdma";
+			reg = <0 0x14006000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+			clocks = <&mmsys CLK_MM_MDP_WDMA0>;
+			iommus = <&iommu M4U_PORT_MDP_WDMA0>;
+		};
+
 		ovl0: ovl@14008000 {
 			compatible = "mediatek,mt8183-disp-ovl";
 			reg = <0 0x14008000 0 0x1000>;
@@ -1513,7 +1586,33 @@
 			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
 			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
 			mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>,
-					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>;
+					      <CMDQ_EVENT_MUTEX_STREAM_DONE1>,
+					      <CMDQ_EVENT_MDP_RDMA0_SOF>,
+					      <CMDQ_EVENT_MDP_RDMA0_EOF>,
+					      <CMDQ_EVENT_MDP_RSZ0_SOF>,
+					      <CMDQ_EVENT_MDP_RSZ1_SOF>,
+					      <CMDQ_EVENT_MDP_TDSHP_SOF>,
+					      <CMDQ_EVENT_MDP_WROT0_SOF>,
+					      <CMDQ_EVENT_MDP_WROT0_EOF>,
+					      <CMDQ_EVENT_MDP_WDMA0_SOF>,
+					      <CMDQ_EVENT_MDP_WDMA0_EOF>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_0>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_1>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_2>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_3>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_4>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_5>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_6>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_7>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_8>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_9>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_10>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_11>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_12>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_13>,
+					      <CMDQ_EVENT_ISP_FRAME_DONE_P2_14>,
+					      <CMDQ_EVENT_WPE_A_DONE>,
+					      <CMDQ_EVENT_SPE_B_DONE>;
 			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
 		};
 
@@ -1538,6 +1637,13 @@
 			power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
 		};
 
+		mdp3_ccorr: mdp3_ccorr@1401c000 {
+			compatible = "mediatek,mt8183-mdp3-ccorr";
+			reg = <0 0x1401c000 0 0x1000>;
+			mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
+			clocks = <&mmsys CLK_MM_MDP_CCORR>;
+		};
+
 		imgsys: syscon@15020000 {
 			compatible = "mediatek,mt8183-imgsys", "syscon";
 			reg = <0 0x15020000 0 0x1000>;
-- 
2.18.0


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^ permalink raw reply related	[flat|nested] 8+ messages in thread

* Re: [PATCH v12 2/3] dts: arm64: mt8183: add Mediatek MDP3 nodes
  2022-03-17 14:56 ` [PATCH v12 2/3] dts: arm64: mt8183: add Mediatek MDP3 nodes Moudy Ho
@ 2022-03-17 15:26   ` AngeloGioacchino Del Regno
  2022-03-18  2:02     ` moudy.ho
  0 siblings, 1 reply; 8+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-03-17 15:26 UTC (permalink / raw)
  To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
	Hans Verkuil, Jernej Skrabec
  Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
	linux-media, devicetree, linux-arm-kernel, linux-mediatek,
	linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
	Maoguang Meng, daoyuan huang, Ping-Hsun Wu, menghui.lin,
	sj.huang, allen-kh.cheng, randy.wu, jason-jh.lin, roy-cw.yeh,
	river.cheng, srv_heupstream,
	Project_Global_Chrome_Upstream_Group

Il 17/03/22 15:56, Moudy Ho ha scritto:
> Add device nodes for Media Data Path 3 (MDP3) modules.
> 
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8183.dtsi | 108 ++++++++++++++++++++++-
>   1 file changed, 107 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index fc6ac2a46324..eaa6dac7768b 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -1389,6 +1389,79 @@
>   			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
>   		};
>   
> +		mdp3_rdma0: mdp3_rdma0@14001000 {

Hello Moudy,

I know, this is already at v12 and I'm truly sorry for noticing this only now,
but that's a bit critical to solve: you can't use underscores in node names (but
you can do it in phandles).

Example:

mdp3_rdma0: mdp3_rdma0@14001000 <-- THIS IS WRONG

mdp3_rdma0: mdp3-rdma0@14001000 <--- THIS IS OK

of course, that's the same also for mdp3-rsz0@..... and the others.

Please fix this both here and in the yaml bindings in patch 1/3!

Sorry again,
Angelo



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^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v12 2/3] dts: arm64: mt8183: add Mediatek MDP3 nodes
  2022-03-17 15:26   ` AngeloGioacchino Del Regno
@ 2022-03-18  2:02     ` moudy.ho
  0 siblings, 0 replies; 8+ messages in thread
From: moudy.ho @ 2022-03-18  2:02 UTC (permalink / raw)
  To: AngeloGioacchino Del Regno, Mauro Carvalho Chehab, Rob Herring,
	Matthias Brugger, Hans Verkuil, Jernej Skrabec
  Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
	linux-media, devicetree, linux-arm-kernel, linux-mediatek,
	linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
	Maoguang Meng, daoyuan huang, Ping-Hsun Wu, menghui.lin,
	sj.huang, allen-kh.cheng, randy.wu, jason-jh.lin, roy-cw.yeh,
	river.cheng, srv_heupstream,
	Project_Global_Chrome_Upstream_Group

On Thu, 2022-03-17 at 16:26 +0100, AngeloGioacchino Del Regno wrote:
> Il 17/03/22 15:56, Moudy Ho ha scritto:
> > Add device nodes for Media Data Path 3 (MDP3) modules.
> > 
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8183.dtsi | 108
> > ++++++++++++++++++++++-
> >   1 file changed, 107 insertions(+), 1 deletion(-)
> > 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > index fc6ac2a46324..eaa6dac7768b 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> > @@ -1389,6 +1389,79 @@
> >   			mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX
> > 0 0x1000>;
> >   		};
> >   
> > +		mdp3_rdma0: mdp3_rdma0@14001000 {
> 
> Hello Moudy,
> 
> I know, this is already at v12 and I'm truly sorry for noticing this
> only now,
> but that's a bit critical to solve: you can't use underscores in node
> names (but
> you can do it in phandles).
> 
> Example:
> 
> mdp3_rdma0: mdp3_rdma0@14001000 <-- THIS IS WRONG
> 
> mdp3_rdma0: mdp3-rdma0@14001000 <--- THIS IS OK
> 
> of course, that's the same also for mdp3-rsz0@..... and the others.
> 
> Please fix this both here and in the yaml bindings in patch 1/3!
> 
> Sorry again,
> Angelo
> 

Hi Angelo,

Thanks for your help in checking and corresting the errors i haven't
found, I'll fix the relevant dts and bindings in the next version.

Thanks,
Moudy


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* Re: [PATCH v12 1/3] dt-binding: mt8183: add Mediatek MDP3 dt-bindings
  2022-03-17 14:56 ` [PATCH v12 1/3] dt-binding: mt8183: add Mediatek MDP3 dt-bindings Moudy Ho
@ 2022-03-30  8:17   ` moudy.ho
  2022-03-31 21:19   ` Rob Herring
  1 sibling, 0 replies; 8+ messages in thread
From: moudy.ho @ 2022-03-30  8:17 UTC (permalink / raw)
  To: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
	Hans Verkuil, Jernej Skrabec
  Cc: Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
	linux-media, devicetree, linux-arm-kernel, linux-mediatek,
	linux-kernel, Alexandre Courbot, tfiga, drinkcat, pihsun, hsinyi,
	AngeloGioacchino Del Regno, Maoguang Meng, daoyuan huang,
	Ping-Hsun Wu, menghui.lin, sj.huang, allen-kh.cheng, randy.wu,
	jason-jh.lin, roy-cw.yeh, river.cheng, srv_heupstream,
	Project_Global_Chrome_Upstream_Group

Hi Rob,

Regarding the redundant hardward index you mentioned in version 11, the
relevant settings have been removed, but not sure if there is anything
else that need to be modified.
Could you help to take a look at this version?

Thanks,
Moudy

On Thu, 2022-03-17 at 22:56 +0800, Moudy Ho wrote:
> This patch adds DT binding documents for Media Data Path 3 (MDP3)
> a unit in multimedia system combined with several components and
> used for scaling and color format convert.
> 
> It can create multiple paths with different functions by assigning
> different components, a simple diagram is as follows:
> 
>   +------------+          +------------+
>   |    RDMA    |          |   ISP[*1]  |
>   +---+--+--+--+          +-----+--+---+
>       A  B  C                   2  1
>       v  v  v                   v  v
>       |  |  |                   |  |
>       |  |  +---------+         |  |
>       |  |            |         |  |
>       |  +-------+    |         |  |
>       |          |    |         |  |
>       |  +-------+----+---------+  |
>       |  |       |    |            |
>       |  |       |    +---------+  |
>       v  v       |              |  |
>       A  2       |              |  |
>     ********     |              |  |
>   **        **   |              |  |
>  *   PQ[*2]   *  |              |  |
>   **        **   |              |  |
>     ********     |              |  |
>       |  |       |              |  |
>       v  v       |              v  v
>       A  2       |              C  1
>   +---+--+---+   |        +-----+--+--+
>   |    RSZ   |   |        |    RSZ    |
>   +---+------+   |        +-----+--+--+
>       D          |              3  4
>       v          |              v  v
>       |          |              |  |
>       |  +-------+              |  |
>       |  |                      |  |
>       |  |  +-------------------+  |
>       |  |  |                      |
>       v  v  v                      v
>       D  B  3                      4
>   +---+--+--+--+         +---------+--+
>   |    WROT    |         |    WDMA    |
>   +------------+         +------------+
> 
> [*1] Direct-link path for camera input
> [*2] A series of picture quality adjustment
>      engines, composed of AAL, CCORR, TDSHP
>      and COLOR
> 
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
>  .../bindings/media/mediatek,mdp3-rdma.yaml    | 214
> ++++++++++++++++++
>  .../bindings/media/mediatek,mdp3-rsz.yaml     |  54 +++++
>  .../bindings/media/mediatek,mdp3-wrot.yaml    |  57 +++++
>  .../bindings/soc/mediatek/mediatek,ccorr.yaml |  47 ++++
>  .../bindings/soc/mediatek/mediatek,wdma.yaml  |  58 +++++
>  5 files changed, 430 insertions(+)
>  create mode 100644
> Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
>  create mode 100644
> Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
>  create mode 100644
> Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
>  create mode 100644
> Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
>  create mode 100644
> Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
> 
> diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-
> rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> rdma.yaml
> new file mode 100644
> index 000000000000..3bf59c3f521f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> @@ -0,0 +1,214 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Read Direct Memory Access
> +
> +maintainers:
> +  - Matthias Brugger <matthias.bgg@gmail.com>
> +
> +description: |
> +  Mediatek Read Direct Memory Access(RDMA) component used to do read
> DMA.
> +  It contains one line buffer to store the sufficient pixel data,
> and
> +  must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +  The 1st RDMA is also used to be a controller node in Media Data
> Path 3(MDP3)
> +  that containing MMSYS, MUTEX, GCE and SCP settings.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          # MDP3 controller node
> +          - const: mediatek,mt8183-mdp3
> +          - const: mediatek,mt8183-mdp3-rdma
> +      - items:
> +          # normal RDMA conponent
> +          - const: mediatek,mt8183-mdp3-rdma
> +
> +  mediatek,scp:
> +    description: |
> +      The node of system control processor (SCP), using
> +      the remoteproc & rpmsg framework.
> +    $ref: '/schemas/types.yaml#/definitions/phandle'
> +    maxItems: 1
> +
> +  mediatek,mdp3-comps:
> +    description: |
> +      MDP subsystem which has direct-link from Image Signal
> Processor(ISP).
> +      When using the camera, the DMA of ISP PASS (DIP) module will
> directly
> +      trigger MDP3 without other control (such as V4L2 M2M) to
> create
> +      corresponding HW path.
> +      The MDP3 controller must set up a series of registers at the
> beginning of
> +      path creation which covering MMSYS, IMGSYS, and MDP3's
> components,
> +      so that data flow can pass through MDP3.
> +      The entire path is briefly described as follows
> +      ISP --+
> +            |
> +            +-> DIP --+
> +      ................|.............................................
> .
> +      (MDP3)          +->IMGI -+-> DL1 ->  RSZ -+-> PATH1 -> WROT
> +                               |            ^   |
> +                               |            |   |
> +                               +-> DL2 -----+   +-> PATH2 -> WDMA
> +                               |
> +                               +---------------------------> EXTO
> +    $ref: '/schemas/types.yaml#/definitions/string-array'
> +    items:
> +      enum:
> +        # MDP direct-link input path selection, create a
> +        # component for path connectedness of HW pipe control
> +        - mediatek,mt8183-mdp3-dl1
> +        - mediatek,mt8183-mdp3-dl2
> +        # MDP direct-link output path selection, create a
> +        # component for path connectedness of HW pipe control
> +        - mediatek,mt8183-mdp3-path1
> +        - mediatek,mt8183-mdp3-path2
> +        # Input DMA of ISP PASS2 (DIP) module for raw image input
> +        - mediatek,mt8183-mdp3-imgi
> +        # Output DMA of ISP PASS2 (DIP) module for YUV image output
> +        - mediatek,mt8183-mdp3-exto
> +
> +  reg:
> +    items:
> +      - description: basic RDMA HW address
> +      - description: MDP direct-link 1st and 2nd input
> +      - description: MDP direct-link 1st output
> +      - description: MDP direct-link 2nd output
> +      - description: ISP input and output
> +
> +  mediatek,gce-client-reg:
> +    $ref: '/schemas/types.yaml#/definitions/phandle-array'
> +    minItems: 1
> +    items:
> +      - description: GCE client for RDMA
> +      - description: GCE client for dl1 and dl2
> +      - description: GCE client for path1
> +      - description: GCE client for path2
> +      - description: GCE client for imgi and exto
> +    description: |
> +      The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce,
> subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a
> client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: RDMA clock
> +      - description: RSZ clock
> +      - description: direck-link TX clock in MDP side
> +      - description: direck-link RX clock in MDP side
> +      - description: direck-link TX clock in ISP side
> +      - description: direck-link RX clock in ISP side
> +
> +  iommus:
> +    maxItems: 1
> +
> +  mediatek,mmsys:
> +    description: The node of mux(multiplexer) controller for HW
> connections.
> +    $ref: '/schemas/types.yaml#/definitions/phandle'
> +
> +  mediatek,mm-mutex:
> +    description: |
> +      Mediatek mutex, namely MUTEX, is used to send the triggers
> signals called
> +      Start Of Frame(SOF) / End Of Frame(EOF) to each sub-modules on
> the data path.
> +      In some SoC, such as mt2701, MUTEX could be a hardware mutex
> which protects
> +      the shadow register.
> +    $ref: '/schemas/types.yaml#/definitions/phandle'
> +
> +  mediatek,mailbox-gce:
> +    description: |
> +      The node of global command engine (GCE), used to read/write
> +      registers with critical time limitation.
> +    $ref: '/schemas/types.yaml#/definitions/phandle'
> +
> +  mboxes:
> +    items:
> +      - description: used for 1st data pipe from RDMA
> +      - description: used for 2nd data pipe from RDMA
> +      - description: used for 3rd data pipe from Direct-Link
> +      - description: used for 4th data pipe from Direct-Link
> +
> +  gce-subsys:
> +    description: |
> +      sub-system id corresponding to the global command engine (GCE)
> +      register address.
> +    $ref: '/schemas/types.yaml#/definitions/phandle-array'
> +
> +if:
> +  properties:
> +    compatible:
> +      contains:
> +        const: mediatek,mt8183-mdp3
> +
> +then:
> +  required:
> +    - mediatek,scp
> +    - mediatek,mmsys
> +    - mediatek,mm-mutex
> +    - mediatek,mailbox-gce
> +    - mboxes
> +    - gce-subsys
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - mediatek,gce-client-reg
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/mt8183-clk.h>
> +    #include <dt-bindings/gce/mt8183-gce.h>
> +    #include <dt-bindings/power/mt8183-power.h>
> +    #include <dt-bindings/memory/mt8183-larb-port.h>
> +
> +    mdp3_rdma0: mdp3_rdma0@14001000 {
> +      compatible = "mediatek,mt8183-mdp3",
> +                   "mediatek,mt8183-mdp3-rdma";
> +      mediatek,scp = <&scp>;
> +      mediatek,mdp3-comps = "mediatek,mt8183-mdp3-dl1",
> +                            "mediatek,mt8183-mdp3-dl2",
> +                            "mediatek,mt8183-mdp3-path1",
> +                            "mediatek,mt8183-mdp3-path2",
> +                            "mediatek,mt8183-mdp3-imgi",
> +                            "mediatek,mt8183-mdp3-exto";
> +      reg = <0x14001000 0x1000>,
> +            <0x14000000 0x1000>,
> +            <0x14005000 0x1000>,
> +            <0x14006000 0x1000>,
> +            <0x15020000 0x1000>;
> +      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000
> 0x1000>,
> +                                <&gce SUBSYS_1400XXXX 0 0x1000>,
> +                                <&gce SUBSYS_1400XXXX 0x5000
> 0x1000>,
> +                                <&gce SUBSYS_1400XXXX 0x6000
> 0x1000>,
> +                                <&gce SUBSYS_1502XXXX 0 0x1000>;
> +      power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> +      clocks = <&mmsys CLK_MM_MDP_RDMA0>,
> +               <&mmsys CLK_MM_MDP_RSZ1>,
> +               <&mmsys CLK_MM_MDP_DL_TXCK>,
> +               <&mmsys CLK_MM_MDP_DL_RX>,
> +               <&mmsys CLK_MM_IPU_DL_TXCK>,
> +               <&mmsys CLK_MM_IPU_DL_RX>;
> +      iommus = <&iommu>;
> +      mediatek,mmsys = <&mmsys>;
> +      mediatek,mm-mutex = <&mutex>;
> +      mediatek,mailbox-gce = <&gce>;
> +      mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
> +               <&gce 21 CMDQ_THR_PRIO_LOWEST>,
> +               <&gce 22 CMDQ_THR_PRIO_LOWEST>,
> +               <&gce 23 CMDQ_THR_PRIO_LOWEST>;
> +      gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
> +                   <&gce 0x14010000 SUBSYS_1401XXXX>,
> +                   <&gce 0x14020000 SUBSYS_1402XXXX>,
> +                   <&gce 0x15020000 SUBSYS_1502XXXX>;
> +    };
> diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-
> rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> rsz.yaml
> new file mode 100644
> index 000000000000..0dcb1a883a8e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> @@ -0,0 +1,54 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Resizer
> +
> +maintainers:
> +  - Matthias Brugger <matthias.bgg@gmail.com>
> +
> +description: |
> +  One of Media Data Path 3 (MDP3) components used to do frame
> resizing.
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - mediatek,mt8183-mdp3-rsz
> +
> +  reg:
> +    maxItems: 1
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by
> gce with
> +      4 arguments defined in this property, such as phandle of gce,
> subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a
> client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +  clocks:
> +    minItems: 1
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/mt8183-clk.h>
> +    #include <dt-bindings/gce/mt8183-gce.h>
> +
> +    mdp3_rsz0: mdp3_rsz0@14003000 {
> +      compatible = "mediatek,mt8183-mdp3-rsz";
> +      reg = <0x14003000 0x1000>;
> +      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000
> 0x1000>;
> +      clocks = <&mmsys CLK_MM_MDP_RSZ0>;
> +    };
> +
> +    mdp3_rsz1: mdp3_rsz1@14004000 {
> +      compatible = "mediatek,mt8183-mdp3-rsz";
> +      reg = <0x14004000 0x1000>;
> +      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000
> 0x1000>;
> +      clocks = <&mmsys CLK_MM_MDP_RSZ1>;
> +    };
> diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-
> wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> wrot.yaml
> new file mode 100644
> index 000000000000..f2c38a9b187d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
> @@ -0,0 +1,57 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Write DMA with Rotation
> +
> +maintainers:
> +  - Matthias Brugger <matthias.bgg@gmail.com>
> +
> +description: |
> +  One of Media Data Path 3 (MDP3) components used to write DMA with
> frame rotation.
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - mediatek,mt8183-mdp3-wrot
> +
> +  reg:
> +    maxItems: 1
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by
> gce with
> +      4 arguments defined in this property, such as phandle of gce,
> subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a
> client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  clocks:
> +    minItems: 1
> +
> +  iommus:
> +    maxItems: 1
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/mt8183-clk.h>
> +    #include <dt-bindings/gce/mt8183-gce.h>
> +    #include <dt-bindings/power/mt8183-power.h>
> +    #include <dt-bindings/memory/mt8183-larb-port.h>
> +
> +    mdp3_wrot0: mdp3_wrot0@14005000 {
> +      compatible = "mediatek,mt8183-mdp3-wrot";
> +      reg = <0x14005000 0x1000>;
> +      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000
> 0x1000>;
> +      power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> +      clocks = <&mmsys CLK_MM_MDP_WROT0>;
> +      iommus = <&iommu>;
> +    };
> diff --git
> a/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
> b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
> new file mode 100644
> index 000000000000..cf23f4f5bd69
> --- /dev/null
> +++
> b/Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
> @@ -0,0 +1,47 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,ccorr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek color correction
> +
> +maintainers:
> +  - Matthias Brugger <matthias.bgg@gmail.com>
> +
> +description: |
> +  Mediatek color correction with 3X3 matrix.
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - mediatek,mt8183-mdp3-ccorr
> +
> +  reg:
> +    maxItems: 1
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by
> gce with
> +      4 arguments defined in this property, such as phandle of gce,
> subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a
> client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +  clocks:
> +    minItems: 1
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/mt8183-clk.h>
> +    #include <dt-bindings/gce/mt8183-gce.h>
> +
> +    mdp3_ccorr: mdp3_ccorr@1401c000 {
> +      compatible = "mediatek,mt8183-mdp3-ccorr";
> +      reg = <0x1401c000 0x1000>;
> +      mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000
> 0x1000>;
> +      clocks = <&mmsys CLK_MM_MDP_CCORR>;
> +    };
> diff --git
> a/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
> b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
> new file mode 100644
> index 000000000000..4057b5232e45
> --- /dev/null
> +++
> b/Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/mediatek/mediatek,wdma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Write Direct Memory Access
> +
> +maintainers:
> +  - Matthias Brugger <matthias.bgg@gmail.com>
> +
> +description: |
> +  Mediatek Write Direct Memory Access(WDMA) component used to write
> +  the data into DMA.
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - mediatek,mt8183-mdp3-wdma
> +
> +  reg:
> +    maxItems: 1
> +
> +  mediatek,gce-client-reg:
> +    description: The register of client driver can be configured by
> gce with
> +      4 arguments defined in this property, such as phandle of gce,
> subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a
> client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    maxItems: 1
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  clocks:
> +    minItems: 1
> +
> +  iommus:
> +    maxItems: 1
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/mt8183-clk.h>
> +    #include <dt-bindings/gce/mt8183-gce.h>
> +    #include <dt-bindings/power/mt8183-power.h>
> +    #include <dt-bindings/memory/mt8183-larb-port.h>
> +
> +    mdp3_wdma: mdp3_wdma@14006000 {
> +      compatible = "mediatek,mt8183-mdp3-wdma";
> +      reg = <0x14006000 0x1000>;
> +      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000
> 0x1000>;
> +      power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> +      clocks = <&mmsys CLK_MM_MDP_WDMA0>;
> +      iommus = <&iommu>;
> +    };


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^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v12 1/3] dt-binding: mt8183: add Mediatek MDP3 dt-bindings
  2022-03-17 14:56 ` [PATCH v12 1/3] dt-binding: mt8183: add Mediatek MDP3 dt-bindings Moudy Ho
  2022-03-30  8:17   ` moudy.ho
@ 2022-03-31 21:19   ` Rob Herring
  2022-04-06  9:23     ` moudy.ho
  1 sibling, 1 reply; 8+ messages in thread
From: Rob Herring @ 2022-03-31 21:19 UTC (permalink / raw)
  To: Moudy Ho
  Cc: Mauro Carvalho Chehab, Matthias Brugger, Hans Verkuil,
	Jernej Skrabec, Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley,
	Laurent Pinchart, linux-media, devicetree, linux-arm-kernel,
	linux-mediatek, linux-kernel, Alexandre Courbot, tfiga, drinkcat,
	pihsun, hsinyi, AngeloGioacchino Del Regno, Maoguang Meng,
	daoyuan huang, Ping-Hsun Wu, menghui.lin, sj.huang,
	allen-kh.cheng, randy.wu, jason-jh.lin, roy-cw.yeh, river.cheng,
	srv_heupstream, Project_Global_Chrome_Upstream_Group

On Thu, Mar 17, 2022 at 10:56:03PM +0800, Moudy Ho wrote:
> This patch adds DT binding documents for Media Data Path 3 (MDP3)
> a unit in multimedia system combined with several components and
> used for scaling and color format convert.
> 
> It can create multiple paths with different functions by assigning
> different components, a simple diagram is as follows:
> 
>   +------------+          +------------+
>   |    RDMA    |          |   ISP[*1]  |
>   +---+--+--+--+          +-----+--+---+
>       A  B  C                   2  1
>       v  v  v                   v  v
>       |  |  |                   |  |
>       |  |  +---------+         |  |
>       |  |            |         |  |
>       |  +-------+    |         |  |
>       |          |    |         |  |
>       |  +-------+----+---------+  |
>       |  |       |    |            |
>       |  |       |    +---------+  |
>       v  v       |              |  |
>       A  2       |              |  |
>     ********     |              |  |
>   **        **   |              |  |
>  *   PQ[*2]   *  |              |  |
>   **        **   |              |  |
>     ********     |              |  |
>       |  |       |              |  |
>       v  v       |              v  v
>       A  2       |              C  1
>   +---+--+---+   |        +-----+--+--+
>   |    RSZ   |   |        |    RSZ    |
>   +---+------+   |        +-----+--+--+
>       D          |              3  4
>       v          |              v  v
>       |          |              |  |
>       |  +-------+              |  |
>       |  |                      |  |
>       |  |  +-------------------+  |
>       |  |  |                      |
>       v  v  v                      v
>       D  B  3                      4
>   +---+--+--+--+         +---------+--+
>   |    WROT    |         |    WDMA    |
>   +------------+         +------------+

Sure seems like you should be using the OF graph binding to describe 
these connections unless all the sub-blocks and their connections are 
fixed across different SoCs.

> 
> [*1] Direct-link path for camera input
> [*2] A series of picture quality adjustment
>      engines, composed of AAL, CCORR, TDSHP
>      and COLOR
> 
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
>  .../bindings/media/mediatek,mdp3-rdma.yaml    | 214 ++++++++++++++++++
>  .../bindings/media/mediatek,mdp3-rsz.yaml     |  54 +++++
>  .../bindings/media/mediatek,mdp3-wrot.yaml    |  57 +++++
>  .../bindings/soc/mediatek/mediatek,ccorr.yaml |  47 ++++
>  .../bindings/soc/mediatek/mediatek,wdma.yaml  |  58 +++++
>  5 files changed, 430 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
>  create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
>  create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
>  create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
>  create mode 100644 Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
> 
> diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> new file mode 100644
> index 000000000000..3bf59c3f521f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> @@ -0,0 +1,214 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Read Direct Memory Access
> +
> +maintainers:
> +  - Matthias Brugger <matthias.bgg@gmail.com>
> +
> +description: |
> +  Mediatek Read Direct Memory Access(RDMA) component used to do read DMA.
> +  It contains one line buffer to store the sufficient pixel data, and
> +  must be siblings to the central MMSYS_CONFIG node.
> +  For a description of the MMSYS_CONFIG binding, see
> +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> +  for details.
> +  The 1st RDMA is also used to be a controller node in Media Data Path 3(MDP3)
> +  that containing MMSYS, MUTEX, GCE and SCP settings.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          # MDP3 controller node
> +          - const: mediatek,mt8183-mdp3
> +          - const: mediatek,mt8183-mdp3-rdma

This does not make sense as a compatible entry. The first string should 
be more specific than the 2nd string. The controller node is a different 
instance of the RDMA block or some s/w designation? Looks like the 
latter to me...


> +      - items:
> +          # normal RDMA conponent
> +          - const: mediatek,mt8183-mdp3-rdma
> +
> +  mediatek,scp:
> +    description: |
> +      The node of system control processor (SCP), using
> +      the remoteproc & rpmsg framework.
> +    $ref: '/schemas/types.yaml#/definitions/phandle'
> +    maxItems: 1
> +
> +  mediatek,mdp3-comps:
> +    description: |
> +      MDP subsystem which has direct-link from Image Signal Processor(ISP).
> +      When using the camera, the DMA of ISP PASS (DIP) module will directly
> +      trigger MDP3 without other control (such as V4L2 M2M) to create
> +      corresponding HW path.
> +      The MDP3 controller must set up a series of registers at the beginning of
> +      path creation which covering MMSYS, IMGSYS, and MDP3's components,
> +      so that data flow can pass through MDP3.
> +      The entire path is briefly described as follows
> +      ISP --+
> +            |
> +            +-> DIP --+
> +      ................|..............................................
> +      (MDP3)          +->IMGI -+-> DL1 ->  RSZ -+-> PATH1 -> WROT
> +                               |            ^   |
> +                               |            |   |
> +                               +-> DL2 -----+   +-> PATH2 -> WDMA
> +                               |
> +                               +---------------------------> EXTO
> +    $ref: '/schemas/types.yaml#/definitions/string-array'
> +    items:
> +      enum:
> +        # MDP direct-link input path selection, create a
> +        # component for path connectedness of HW pipe control
> +        - mediatek,mt8183-mdp3-dl1
> +        - mediatek,mt8183-mdp3-dl2
> +        # MDP direct-link output path selection, create a
> +        # component for path connectedness of HW pipe control
> +        - mediatek,mt8183-mdp3-path1
> +        - mediatek,mt8183-mdp3-path2
> +        # Input DMA of ISP PASS2 (DIP) module for raw image input
> +        - mediatek,mt8183-mdp3-imgi
> +        # Output DMA of ISP PASS2 (DIP) module for YUV image output
> +        - mediatek,mt8183-mdp3-exto
> +
> +  reg:
> +    items:
> +      - description: basic RDMA HW address
> +      - description: MDP direct-link 1st and 2nd input
> +      - description: MDP direct-link 1st output
> +      - description: MDP direct-link 2nd output
> +      - description: ISP input and output
> +
> +  mediatek,gce-client-reg:
> +    $ref: '/schemas/types.yaml#/definitions/phandle-array'
> +    minItems: 1
> +    items:
> +      - description: GCE client for RDMA
> +      - description: GCE client for dl1 and dl2
> +      - description: GCE client for path1
> +      - description: GCE client for path2
> +      - description: GCE client for imgi and exto
> +    description: |
> +      The register of client driver can be configured by gce with
> +      4 arguments defined in this property, such as phandle of gce, subsys id,
> +      register offset and size. Each GCE subsys id is mapping to a client
> +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  clocks:
> +    items:
> +      - description: RDMA clock
> +      - description: RSZ clock
> +      - description: direck-link TX clock in MDP side
> +      - description: direck-link RX clock in MDP side
> +      - description: direck-link TX clock in ISP side
> +      - description: direck-link RX clock in ISP side
> +
> +  iommus:
> +    maxItems: 1
> +
> +  mediatek,mmsys:
> +    description: The node of mux(multiplexer) controller for HW connections.
> +    $ref: '/schemas/types.yaml#/definitions/phandle'
> +
> +  mediatek,mm-mutex:
> +    description: |
> +      Mediatek mutex, namely MUTEX, is used to send the triggers signals called
> +      Start Of Frame(SOF) / End Of Frame(EOF) to each sub-modules on the data path.
> +      In some SoC, such as mt2701, MUTEX could be a hardware mutex which protects
> +      the shadow register.
> +    $ref: '/schemas/types.yaml#/definitions/phandle'
> +
> +  mediatek,mailbox-gce:
> +    description: |
> +      The node of global command engine (GCE), used to read/write
> +      registers with critical time limitation.
> +    $ref: '/schemas/types.yaml#/definitions/phandle'
> +
> +  mboxes:
> +    items:
> +      - description: used for 1st data pipe from RDMA
> +      - description: used for 2nd data pipe from RDMA
> +      - description: used for 3rd data pipe from Direct-Link
> +      - description: used for 4th data pipe from Direct-Link
> +
> +  gce-subsys:

Vendor prefix needed.

> +    description: |
> +      sub-system id corresponding to the global command engine (GCE)
> +      register address.
> +    $ref: '/schemas/types.yaml#/definitions/phandle-array'
> +
> +if:
> +  properties:
> +    compatible:
> +      contains:
> +        const: mediatek,mt8183-mdp3
> +
> +then:
> +  required:
> +    - mediatek,scp
> +    - mediatek,mmsys
> +    - mediatek,mm-mutex
> +    - mediatek,mailbox-gce

Note that if there's only 1 instance of these blocks, you can just find 
them by compatible and don't need a property.

> +    - mboxes
> +    - gce-subsys
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - mediatek,gce-client-reg
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/mt8183-clk.h>
> +    #include <dt-bindings/gce/mt8183-gce.h>
> +    #include <dt-bindings/power/mt8183-power.h>
> +    #include <dt-bindings/memory/mt8183-larb-port.h>
> +
> +    mdp3_rdma0: mdp3_rdma0@14001000 {
> +      compatible = "mediatek,mt8183-mdp3",
> +                   "mediatek,mt8183-mdp3-rdma";
> +      mediatek,scp = <&scp>;
> +      mediatek,mdp3-comps = "mediatek,mt8183-mdp3-dl1",
> +                            "mediatek,mt8183-mdp3-dl2",
> +                            "mediatek,mt8183-mdp3-path1",
> +                            "mediatek,mt8183-mdp3-path2",
> +                            "mediatek,mt8183-mdp3-imgi",
> +                            "mediatek,mt8183-mdp3-exto";
> +      reg = <0x14001000 0x1000>,
> +            <0x14000000 0x1000>,
> +            <0x14005000 0x1000>,
> +            <0x14006000 0x1000>,
> +            <0x15020000 0x1000>;
> +      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>,
> +                                <&gce SUBSYS_1400XXXX 0 0x1000>,
> +                                <&gce SUBSYS_1400XXXX 0x5000 0x1000>,
> +                                <&gce SUBSYS_1400XXXX 0x6000 0x1000>,
> +                                <&gce SUBSYS_1502XXXX 0 0x1000>;
> +      power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> +      clocks = <&mmsys CLK_MM_MDP_RDMA0>,
> +               <&mmsys CLK_MM_MDP_RSZ1>,
> +               <&mmsys CLK_MM_MDP_DL_TXCK>,
> +               <&mmsys CLK_MM_MDP_DL_RX>,
> +               <&mmsys CLK_MM_IPU_DL_TXCK>,
> +               <&mmsys CLK_MM_IPU_DL_RX>;
> +      iommus = <&iommu>;
> +      mediatek,mmsys = <&mmsys>;
> +      mediatek,mm-mutex = <&mutex>;
> +      mediatek,mailbox-gce = <&gce>;
> +      mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
> +               <&gce 21 CMDQ_THR_PRIO_LOWEST>,
> +               <&gce 22 CMDQ_THR_PRIO_LOWEST>,
> +               <&gce 23 CMDQ_THR_PRIO_LOWEST>;
> +      gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
> +                   <&gce 0x14010000 SUBSYS_1401XXXX>,
> +                   <&gce 0x14020000 SUBSYS_1402XXXX>,
> +                   <&gce 0x15020000 SUBSYS_1502XXXX>;
> +    };

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^ permalink raw reply	[flat|nested] 8+ messages in thread

* Re: [PATCH v12 1/3] dt-binding: mt8183: add Mediatek MDP3 dt-bindings
  2022-03-31 21:19   ` Rob Herring
@ 2022-04-06  9:23     ` moudy.ho
  0 siblings, 0 replies; 8+ messages in thread
From: moudy.ho @ 2022-04-06  9:23 UTC (permalink / raw)
  To: Rob Herring
  Cc: Mauro Carvalho Chehab, Matthias Brugger, Hans Verkuil,
	Jernej Skrabec, Chun-Kuang Hu, Geert Uytterhoeven, Rob Landley,
	Laurent Pinchart, linux-media, devicetree, linux-arm-kernel,
	linux-mediatek, linux-kernel, Alexandre Courbot, tfiga, drinkcat,
	pihsun, hsinyi, AngeloGioacchino Del Regno, Maoguang Meng,
	daoyuan huang, Ping-Hsun Wu, menghui.lin, sj.huang,
	allen-kh.cheng, randy.wu, jason-jh.lin, roy-cw.yeh, river.cheng,
	srv_heupstream, Project_Global_Chrome_Upstream_Group

Hi Rob,

Thanks for your advises, some responses are as follows.

On Thu, 2022-03-31 at 16:19 -0500, Rob Herring wrote:
> On Thu, Mar 17, 2022 at 10:56:03PM +0800, Moudy Ho wrote:
> > This patch adds DT binding documents for Media Data Path 3 (MDP3)
> > a unit in multimedia system combined with several components and
> > used for scaling and color format convert.
> > 
> > It can create multiple paths with different functions by assigning
> > different components, a simple diagram is as follows:
> > 
> >   +------------+          +------------+
> >   |    RDMA    |          |   ISP[*1]  |
> >   +---+--+--+--+          +-----+--+---+
> >       A  B  C                   2  1
> >       v  v  v                   v  v
> >       |  |  |                   |  |
> >       |  |  +---------+         |  |
> >       |  |            |         |  |
> >       |  +-------+    |         |  |
> >       |          |    |         |  |
> >       |  +-------+----+---------+  |
> >       |  |       |    |            |
> >       |  |       |    +---------+  |
> >       v  v       |              |  |
> >       A  2       |              |  |
> >     ********     |              |  |
> >   **        **   |              |  |
> >  *   PQ[*2]   *  |              |  |
> >   **        **   |              |  |
> >     ********     |              |  |
> >       |  |       |              |  |
> >       v  v       |              v  v
> >       A  2       |              C  1
> >   +---+--+---+   |        +-----+--+--+
> >   |    RSZ   |   |        |    RSZ    |
> >   +---+------+   |        +-----+--+--+
> >       D          |              3  4
> >       v          |              v  v
> >       |          |              |  |
> >       |  +-------+              |  |
> >       |  |                      |  |
> >       |  |  +-------------------+  |
> >       |  |  |                      |
> >       v  v  v                      v
> >       D  B  3                      4
> >   +---+--+--+--+         +---------+--+
> >   |    WROT    |         |    WDMA    |
> >   +------------+         +------------+
> 
> Sure seems like you should be using the OF graph binding to describe 
> these connections unless all the sub-blocks and their connections
> are 
> fixed across different SoCs.
> 

Sorry for the misunderstanding, this diagram was originally used to
illustrate the design principle of the previous version, but now the
relevant routing information has been moved from MDP3 to MMSYS.
The original hardware index is designed for MDP3 to control routing
settings, but at your reminder, we check that this control is actually
more suitable to be placed in MMSYS which directly sets the mux
register.
Since the final control is in the upper module MMSYS and MDP3 is only a
component provider, should the relevant block diagram be removed from
MDP3 to avoid further misunderstanding.

> > 
> > [*1] Direct-link path for camera input
> > [*2] A series of picture quality adjustment
> >      engines, composed of AAL, CCORR, TDSHP
> >      and COLOR
> > 
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > ---
> >  .../bindings/media/mediatek,mdp3-rdma.yaml    | 214
> > ++++++++++++++++++
> >  .../bindings/media/mediatek,mdp3-rsz.yaml     |  54 +++++
> >  .../bindings/media/mediatek,mdp3-wrot.yaml    |  57 +++++
> >  .../bindings/soc/mediatek/mediatek,ccorr.yaml |  47 ++++
> >  .../bindings/soc/mediatek/mediatek,wdma.yaml  |  58 +++++
> >  5 files changed, 430 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> >  create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> >  create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
> >  create mode 100644
> > Documentation/devicetree/bindings/soc/mediatek/mediatek,ccorr.yaml
> >  create mode 100644
> > Documentation/devicetree/bindings/soc/mediatek/mediatek,wdma.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rdma.yaml
> > new file mode 100644
> > index 000000000000..3bf59c3f521f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rdma.yaml
> > @@ -0,0 +1,214 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: 
> > https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml*__;Iw!!CTRNKA9wMg0ARbw!wgkVc9UZ_DrFo3wSkfSUMtOET9ehz_854vK450j_jmVDVRaLrLgDaCKPPbJWNtWX$
> >  
> > +$schema: 
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!wgkVc9UZ_DrFo3wSkfSUMtOET9ehz_854vK450j_jmVDVRaLrLgDaCKPPZdLY-1x$
> >  
> > +
> > +title: Mediatek Read Direct Memory Access
> > +
> > +maintainers:
> > +  - Matthias Brugger <matthias.bgg@gmail.com>
> > +
> > +description: |
> > +  Mediatek Read Direct Memory Access(RDMA) component used to do
> > read DMA.
> > +  It contains one line buffer to store the sufficient pixel data,
> > and
> > +  must be siblings to the central MMSYS_CONFIG node.
> > +  For a description of the MMSYS_CONFIG binding, see
> > +  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.ya
> > ml
> > +  for details.
> > +  The 1st RDMA is also used to be a controller node in Media Data
> > Path 3(MDP3)
> > +  that containing MMSYS, MUTEX, GCE and SCP settings.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          # MDP3 controller node
> > +          - const: mediatek,mt8183-mdp3
> > +          - const: mediatek,mt8183-mdp3-rdma
> 
> This does not make sense as a compatible entry. The first string
> should 
> be more specific than the 2nd string. The controller node is a
> different 
> instance of the RDMA block or some s/w designation? Looks like the 
> latter to me...
> 
> 

This is exactly what you supposed, and there is currently only one RDMA
and should not make additional distinctions. This part will be
corrected in the next version

> > Thanks for the reminder, this part should not be designed as a
> > multi-instance scenario, and the relevant design should be left to
> > present in future chips.
> > +      - items:
> > +          # normal RDMA conponent
> > +          - const: mediatek,mt8183-mdp3-rdma
> > +
> > +  mediatek,scp:
> > +    description: |
> > +      The node of system control processor (SCP), using
> > +      the remoteproc & rpmsg framework.
> > +    $ref: '/schemas/types.yaml#/definitions/phandle'
> > +    maxItems: 1
> > +
> > +  mediatek,mdp3-comps:
> > +    description: |
> > +      MDP subsystem which has direct-link from Image Signal
> > Processor(ISP).
> > +      When using the camera, the DMA of ISP PASS (DIP) module will
> > directly
> > +      trigger MDP3 without other control (such as V4L2 M2M) to
> > create
> > +      corresponding HW path.
> > +      The MDP3 controller must set up a series of registers at the
> > beginning of
> > +      path creation which covering MMSYS, IMGSYS, and MDP3's
> > components,
> > +      so that data flow can pass through MDP3.
> > +      The entire path is briefly described as follows
> > +      ISP --+
> > +            |
> > +            +-> DIP --+
> > +      ................|...........................................
> > ...
> > +      (MDP3)          +->IMGI -+-> DL1 ->  RSZ -+-> PATH1 -> WROT
> > +                               |            ^   |
> > +                               |            |   |
> > +                               +-> DL2 -----+   +-> PATH2 -> WDMA
> > +                               |
> > +                               +---------------------------> EXTO
> > +    $ref: '/schemas/types.yaml#/definitions/string-array'
> > +    items:
> > +      enum:
> > +        # MDP direct-link input path selection, create a
> > +        # component for path connectedness of HW pipe control
> > +        - mediatek,mt8183-mdp3-dl1
> > +        - mediatek,mt8183-mdp3-dl2
> > +        # MDP direct-link output path selection, create a
> > +        # component for path connectedness of HW pipe control
> > +        - mediatek,mt8183-mdp3-path1
> > +        - mediatek,mt8183-mdp3-path2
> > +        # Input DMA of ISP PASS2 (DIP) module for raw image input
> > +        - mediatek,mt8183-mdp3-imgi
> > +        # Output DMA of ISP PASS2 (DIP) module for YUV image
> > output
> > +        - mediatek,mt8183-mdp3-exto
> > +
> > +  reg:
> > +    items:
> > +      - description: basic RDMA HW address
> > +      - description: MDP direct-link 1st and 2nd input
> > +      - description: MDP direct-link 1st output
> > +      - description: MDP direct-link 2nd output
> > +      - description: ISP input and output
> > +
> > +  mediatek,gce-client-reg:
> > +    $ref: '/schemas/types.yaml#/definitions/phandle-array'
> > +    minItems: 1
> > +    items:
> > +      - description: GCE client for RDMA
> > +      - description: GCE client for dl1 and dl2
> > +      - description: GCE client for path1
> > +      - description: GCE client for path2
> > +      - description: GCE client for imgi and exto
> > +    description: |
> > +      The register of client driver can be configured by gce with
> > +      4 arguments defined in this property, such as phandle of
> > gce, subsys id,
> > +      register offset and size. Each GCE subsys id is mapping to a
> > client
> > +      defined in the header include/dt-bindings/gce/<chip>-gce.h.
> > +
> > +  power-domains:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    items:
> > +      - description: RDMA clock
> > +      - description: RSZ clock
> > +      - description: direck-link TX clock in MDP side
> > +      - description: direck-link RX clock in MDP side
> > +      - description: direck-link TX clock in ISP side
> > +      - description: direck-link RX clock in ISP side
> > +
> > +  iommus:
> > +    maxItems: 1
> > +
> > +  mediatek,mmsys:
> > +    description: The node of mux(multiplexer) controller for HW
> > connections.
> > +    $ref: '/schemas/types.yaml#/definitions/phandle'
> > +
> > +  mediatek,mm-mutex:
> > +    description: |
> > +      Mediatek mutex, namely MUTEX, is used to send the triggers
> > signals called
> > +      Start Of Frame(SOF) / End Of Frame(EOF) to each sub-modules
> > on the data path.
> > +      In some SoC, such as mt2701, MUTEX could be a hardware mutex
> > which protects
> > +      the shadow register.
> > +    $ref: '/schemas/types.yaml#/definitions/phandle'
> > +
> > +  mediatek,mailbox-gce:
> > +    description: |
> > +      The node of global command engine (GCE), used to read/write
> > +      registers with critical time limitation.
> > +    $ref: '/schemas/types.yaml#/definitions/phandle'
> > +
> > +  mboxes:
> > +    items:
> > +      - description: used for 1st data pipe from RDMA
> > +      - description: used for 2nd data pipe from RDMA
> > +      - description: used for 3rd data pipe from Direct-Link
> > +      - description: used for 4th data pipe from Direct-Link
> > +
> > +  gce-subsys:
> 
> Vendor prefix needed.
> 

Thanks for the reminder, this should be removed directly and replaced
by "mediatek,gce-client-reg".

> > +    description: |
> > +      sub-system id corresponding to the global command engine
> > (GCE)
> > +      register address.
> > +    $ref: '/schemas/types.yaml#/definitions/phandle-array'
> > +
> > +if:
> > +  properties:
> > +    compatible:
> > +      contains:
> > +        const: mediatek,mt8183-mdp3
> > +
> > +then:
> > +  required:
> > +    - mediatek,scp
> > +    - mediatek,mmsys
> > +    - mediatek,mm-mutex
> > +    - mediatek,mailbox-gce
> 
> Note that if there's only 1 instance of these blocks, you can just
> find 
> them by compatible and don't need a property.
> 

Thanks for the correction, this part should not be designed as a multi-
instance scenario, and the relevant design should be left to present in
future chips.

Thanks,
Moudy
> > +    - mboxes
> > +    - gce-subsys
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +  - mediatek,gce-client-reg
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/mt8183-clk.h>
> > +    #include <dt-bindings/gce/mt8183-gce.h>
> > +    #include <dt-bindings/power/mt8183-power.h>
> > +    #include <dt-bindings/memory/mt8183-larb-port.h>
> > +
> > +    mdp3_rdma0: mdp3_rdma0@14001000 {
> > +      compatible = "mediatek,mt8183-mdp3",
> > +                   "mediatek,mt8183-mdp3-rdma";
> > +      mediatek,scp = <&scp>;
> > +      mediatek,mdp3-comps = "mediatek,mt8183-mdp3-dl1",
> > +                            "mediatek,mt8183-mdp3-dl2",
> > +                            "mediatek,mt8183-mdp3-path1",
> > +                            "mediatek,mt8183-mdp3-path2",
> > +                            "mediatek,mt8183-mdp3-imgi",
> > +                            "mediatek,mt8183-mdp3-exto";
> > +      reg = <0x14001000 0x1000>,
> > +            <0x14000000 0x1000>,
> > +            <0x14005000 0x1000>,
> > +            <0x14006000 0x1000>,
> > +            <0x15020000 0x1000>;
> > +      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000
> > 0x1000>,
> > +                                <&gce SUBSYS_1400XXXX 0 0x1000>,
> > +                                <&gce SUBSYS_1400XXXX 0x5000
> > 0x1000>,
> > +                                <&gce SUBSYS_1400XXXX 0x6000
> > 0x1000>,
> > +                                <&gce SUBSYS_1502XXXX 0 0x1000>;
> > +      power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> > +      clocks = <&mmsys CLK_MM_MDP_RDMA0>,
> > +               <&mmsys CLK_MM_MDP_RSZ1>,
> > +               <&mmsys CLK_MM_MDP_DL_TXCK>,
> > +               <&mmsys CLK_MM_MDP_DL_RX>,
> > +               <&mmsys CLK_MM_IPU_DL_TXCK>,
> > +               <&mmsys CLK_MM_IPU_DL_RX>;
> > +      iommus = <&iommu>;
> > +      mediatek,mmsys = <&mmsys>;
> > +      mediatek,mm-mutex = <&mutex>;
> > +      mediatek,mailbox-gce = <&gce>;
> > +      mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
> > +               <&gce 21 CMDQ_THR_PRIO_LOWEST>,
> > +               <&gce 22 CMDQ_THR_PRIO_LOWEST>,
> > +               <&gce 23 CMDQ_THR_PRIO_LOWEST>;
> > +      gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
> > +                   <&gce 0x14010000 SUBSYS_1401XXXX>,
> > +                   <&gce 0x14020000 SUBSYS_1402XXXX>,
> > +                   <&gce 0x15020000 SUBSYS_1502XXXX>;
> > +    };


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^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2022-04-06  9:32 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-17 14:56 [PATCH v12 0/3] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
2022-03-17 14:56 ` [PATCH v12 1/3] dt-binding: mt8183: add Mediatek MDP3 dt-bindings Moudy Ho
2022-03-30  8:17   ` moudy.ho
2022-03-31 21:19   ` Rob Herring
2022-04-06  9:23     ` moudy.ho
2022-03-17 14:56 ` [PATCH v12 2/3] dts: arm64: mt8183: add Mediatek MDP3 nodes Moudy Ho
2022-03-17 15:26   ` AngeloGioacchino Del Regno
2022-03-18  2:02     ` moudy.ho

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