From: Lokesh Vutla <lokeshvutla@ti.com>
To: Tony Lindgren <tony@atomide.com>
Cc: Nishanth Menon <nm@ti.com>,
Device Tree Mailing List <devicetree@vger.kernel.org>,
jason@lakedaemon.net, Peter Ujfalusi <peter.ujfalusi@ti.com>,
marc.zyngier@arm.com, Sekhar Nori <nsekhar@ti.com>,
linux-kernel@vger.kernel.org, Tero Kristo <t-kristo@ti.com>,
Rob Herring <robh+dt@kernel.org>,
Santosh Shilimkar <ssantosh@kernel.org>,
tglx@linutronix.de,
Linux ARM Mailing List <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v5 05/10] dt-bindings: irqchip: Introduce TISCI Interrupt router bindings
Date: Thu, 14 Feb 2019 14:10:02 +0530 [thread overview]
Message-ID: <821ab540-469a-2166-9346-9cc0dec8ffbe@ti.com> (raw)
In-Reply-To: <20190213153215.GT5720@atomide.com>
On 13/02/19 9:02 PM, Tony Lindgren wrote:
> * Lokesh Vutla <lokeshvutla@ti.com> [190213 04:23]:
>> Hi Tony,
>>
>> On 12/02/19 10:00 PM, Tony Lindgren wrote:
>>> Hi,
>>>
>>> * Lokesh Vutla <lokeshvutla@ti.com> [190212 07:43]:
>>>> +The Interrupt Router (INTR) module provides a mechanism to route M
>>>> +interrupt inputs to N interrupt outputs, where all M inputs are selectable
>>>> +to be driven per N output. There is one register per output (MUXCNTL_N) that
>>>> +controls the selection.
>>>> +
>>>> +
>>>> + Interrupt Router
>>>> + +----------------------+
>>>> + | Inputs Outputs |
>>>> + +-------+ | +------+ |
>>>> + | GPIO |----------->| | irq0 | | Host IRQ
>>>> + +-------+ | +------+ | controller
>>>> + | . +-----+ | +-------+
>>>> + +-------+ | . | 0 | |----->| IRQ |
>>>> + | INTA |----------->| . +-----+ | +-------+
>>>> + +-------+ | . . |
>>>> + | +------+ . |
>>>> + | | irqM | +-----+ |
>>>> + | +------+ | N | |
>>>> + | +-----+ |
>>>> + +----------------------+
>>>
>>> Is this always one-to-one mapping or can the same interrupt be routed to
>>> multiple targets like to the SoC and some coprocessor?
>>
>> Yes, it is always one-to-one. Output of INTR can only be attached to one of the
>> processor.
>
> OK
>
>>>> +Configuration of these MUXCNTL_N registers is done by a system controller
>>>> +(like the Device Memory and Security Controller on K3 AM654 SoC). System
>>>> +controller will keep track of the used and unused registers within the Router.
>>>> +Driver should request the system controller to get the range of GIC IRQs
>>>> +assigned to the requesting hosts. It is the drivers responsibility to keep
>>>> +track of Host IRQs.
>>>> +
>>>> +Communication between the host processor running an OS and the system
>>>> +controller happens through a protocol called TI System Control Interface
>>>> +(TISCI protocol). For more details refer:
>>>> +Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
>>>
>>> Care to describe a bit why the interrupts need to be routed by a system
>>> controller?
>>
>> K3 architecture defines a heterogeneous system where multiple heterogeneous
>> cores are serving its own usecases. Given that there are multiple ways in which
>> a device IRQ can be routed using INTR, like either it can be routed to HLOS
>> core(A53 int this case) or it can be routed to any other coprocessor available
>> in the system(like R5). If every sw running in each co-processor is allowed to
>> program this INTR then there is a high probability that one sw executing on one
>> core can damage other heterogeneous core. Mainly to avoid this damage the
>> configuration of all the INTRs and INTAs are done in a centralized place(sysfw).
>> Any user for programming its IRQ route should send a message to sysfw with the
>> parameters. These parameters are policed by sysfw and does the configuration.
>
> OK so maybe update the description along those lines saying it's
> a shared piece of hardware between various independent SoC
> clusters which may or may not be running Linux.
IMHO, SoC integration is out of scope of this document. If you insist I can add
the details.
Thanks and regards,
Lokesh
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next prev parent reply other threads:[~2019-02-14 8:40 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-12 7:42 [PATCH v5 00/10] Add support for TISCI irqchip drivers Lokesh Vutla
2019-02-12 7:42 ` [PATCH v5 01/10] firmware: ti_sci: Add support to get TISCI handle using of_phandle Lokesh Vutla
2019-02-12 7:42 ` [PATCH v5 02/10] firmware: ti_sci: Add support for RM core ops Lokesh Vutla
2019-02-12 7:42 ` [PATCH v5 03/10] firmware: ti_sci: Add support for IRQ management Lokesh Vutla
2019-02-12 7:42 ` [PATCH v5 04/10] firmware: ti_sci: Add RM mapping table for am654 Lokesh Vutla
2019-02-12 7:42 ` [PATCH v5 05/10] dt-bindings: irqchip: Introduce TISCI Interrupt router bindings Lokesh Vutla
2019-02-12 16:22 ` Tony Lindgren
2019-02-13 4:25 ` Lokesh Vutla
2019-02-13 15:26 ` Tony Lindgren
2019-02-13 20:40 ` Rob Herring
2019-02-14 8:38 ` Lokesh Vutla
2019-02-14 15:41 ` Tony Lindgren
2019-02-14 17:32 ` Lokesh Vutla
2019-02-14 17:46 ` Tony Lindgren
2019-02-14 18:02 ` Lokesh Vutla
2019-02-15 16:16 ` Tony Lindgren
2019-02-16 3:29 ` Lokesh Vutla
2019-02-18 14:32 ` Tony Lindgren
2019-02-19 8:51 ` Lokesh Vutla
2019-02-19 15:35 ` Tony Lindgren
2019-02-19 16:19 ` Lokesh Vutla
2019-02-19 17:11 ` Tony Lindgren
2019-02-19 17:56 ` Tony Lindgren
2019-02-20 5:53 ` Lokesh Vutla
2019-02-20 16:36 ` Tony Lindgren
2019-02-20 17:17 ` Lokesh Vutla
2019-02-12 16:30 ` Tony Lindgren
2019-02-13 4:22 ` Lokesh Vutla
2019-02-13 15:32 ` Tony Lindgren
2019-02-14 8:40 ` Lokesh Vutla [this message]
2019-02-14 15:42 ` Tony Lindgren
2019-02-16 3:30 ` Lokesh Vutla
2019-02-18 14:35 ` Tony Lindgren
2019-02-22 10:10 ` Peter Ujfalusi
2019-02-18 15:12 ` Marc Zyngier
2019-02-18 15:27 ` Lokesh Vutla
2019-02-12 7:42 ` [PATCH v5 06/10] irqchip: ti-sci-intr: Add support for Interrupt Router driver Lokesh Vutla
2019-02-18 15:52 ` Marc Zyngier
2019-02-20 13:17 ` Lokesh Vutla
2019-03-19 12:44 ` Lokesh Vutla
2019-02-12 7:42 ` [PATCH v5 07/10] dt-bindings: irqchip: Introduce TISCI Interrupt Aggregator bindings Lokesh Vutla
2019-02-12 7:42 ` [PATCH v5 08/10] irqchip: ti-sci-inta: Add support for Interrupt Aggregator driver Lokesh Vutla
2019-02-12 7:42 ` [PATCH v5 09/10] soc: ti: Add MSI domain support for K3 Interrupt Aggregator Lokesh Vutla
2019-02-13 16:41 ` Tony Lindgren
2019-02-12 7:42 ` [PATCH v5 10/10] soc: ti: am6: Enable interrupt controller drivers Lokesh Vutla
2019-02-16 3:37 ` [PATCH v5 00/10] Add support for TISCI irqchip drivers Lokesh Vutla
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