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Wed, 26 Jun 2019 23:57:49 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.1.6-730-g63f2c3b-fmstable-20190622v1 Mime-Version: 1.0 Message-Id: <835ac4e3-6ee4-4c3f-913b-93629d7e8080@www.fastmail.com> In-Reply-To: References: <20190626071430.28556-1-andrew@aj.id.au> <20190626071430.28556-6-andrew@aj.id.au> Date: Thu, 27 Jun 2019 13:27:49 +0930 From: "Andrew Jeffery" To: "Joel Stanley" Subject: =?UTF-8?Q?Re:_[PATCH_5/8]_pinctrl:_aspeed:_Correct_comment_that_is_no_lo?= =?UTF-8?Q?nger_true?= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190627_045901_277222_34078D52 X-CRM114-Status: GOOD ( 16.77 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree , Ryan Chen , linux-aspeed@lists.ozlabs.org, Linus Walleij , Linux Kernel Mailing List , linux-gpio@vger.kernel.org, Rob Herring , OpenBMC Maillist , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 27 Jun 2019, at 13:00, Joel Stanley wrote: > On Wed, 26 Jun 2019 at 07:16, Andrew Jeffery wrote: > > > > We have handled the GFX register case for quite some time now. > > > > Signed-off-by: Andrew Jeffery > > --- > > drivers/pinctrl/aspeed/pinctrl-aspeed.h | 3 +-- > > 1 file changed, 1 insertion(+), 2 deletions(-) > > > > diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h > > index 4b06ddbc6aec..c5918c4a087c 100644 > > --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h > > +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h > > @@ -240,8 +240,7 @@ > > * opposed to naming them e.g. PINMUX_CTRL_[0-9]). Further, signal expressions > > * reference registers beyond those dedicated to pinmux, such as the system > > * reset control and MAC clock configuration registers. The AST2500 goes a step > > AST2600 too? No mention of the GFX block in the pinctrl table for the 2600, it appears the pinmux state is entirely determined by SCU registers. > > Acked-by: Joel Stanley Cheers, Andrew > > > - * further and references registers in the graphics IP block, but that isn't > > - * handled yet. > > + * further and references registers in the graphics IP block. > > */ > > #define SCU2C 0x2C /* Misc. Control Register */ > > #define SCU3C 0x3C /* System Reset Control/Status Register */ > > -- > > 2.20.1 > > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel