* [PATCH 1/3] arm64: Add MIDR value for KRYO4XX gold CPU cores
2020-06-30 18:00 [PATCH 0/3] Add Kryo4xx gold and silver cores to applicable errata list Sai Prakash Ranjan
@ 2020-06-30 18:00 ` Sai Prakash Ranjan
2020-06-30 18:00 ` [PATCH 2/3] arm64: Add KRYO4XX gold CPU cores to erratum list 1463225 and 1418040 Sai Prakash Ranjan
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Sai Prakash Ranjan @ 2020-06-30 18:00 UTC (permalink / raw)
To: Will Deacon, Catalin Marinas, Marc Zyngier, Suzuki K Poulose,
Mark Rutland, Douglas Anderson, Stephen Boyd
Cc: Sai Prakash Ranjan, Jeffrey Hugo, Andre Przywara, linux-kernel,
linux-arm-msm, linux-arm-kernel
Add MIDR value for KRYO4XX gold/big CPU cores which are
used in Qualcomm Technologies, Inc. SoCs. This will be
used to identify and apply erratum which are applicable
for these CPU cores.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index a87a93f67671..7219cddeba66 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -86,6 +86,7 @@
#define QCOM_CPU_PART_FALKOR 0xC00
#define QCOM_CPU_PART_KRYO 0x200
#define QCOM_CPU_PART_KRYO_3XX_SILVER 0x803
+#define QCOM_CPU_PART_KRYO_4XX_GOLD 0x804
#define QCOM_CPU_PART_KRYO_4XX_SILVER 0x805
#define NVIDIA_CPU_PART_DENVER 0x003
@@ -114,6 +115,7 @@
#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)
#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)
#define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER)
+#define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD)
#define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER)
#define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER)
#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
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^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 2/3] arm64: Add KRYO4XX gold CPU cores to erratum list 1463225 and 1418040
2020-06-30 18:00 [PATCH 0/3] Add Kryo4xx gold and silver cores to applicable errata list Sai Prakash Ranjan
2020-06-30 18:00 ` [PATCH 1/3] arm64: Add MIDR value for KRYO4XX gold CPU cores Sai Prakash Ranjan
@ 2020-06-30 18:00 ` Sai Prakash Ranjan
2020-06-30 18:00 ` [PATCH 3/3] arm64: Add KRYO4XX silver CPU cores to erratum list 1530923 and 1024718 Sai Prakash Ranjan
2020-07-03 16:35 ` [PATCH 0/3] Add Kryo4xx gold and silver cores to applicable errata list Will Deacon
3 siblings, 0 replies; 6+ messages in thread
From: Sai Prakash Ranjan @ 2020-06-30 18:00 UTC (permalink / raw)
To: Will Deacon, Catalin Marinas, Marc Zyngier, Suzuki K Poulose,
Mark Rutland, Douglas Anderson, Stephen Boyd
Cc: Sai Prakash Ranjan, Jeffrey Hugo, Andre Przywara, linux-kernel,
linux-arm-msm, linux-arm-kernel
KRYO4XX gold/big CPU core revisions r0p0 to r3p1 are affected by
erratum 1463225 and 1418040, so add them to the respective list.
The variant and revision bits are implementation defined and are
different from the their Cortex CPU counterparts on which they are
based on, i.e., (r0p0 to r3p1) is equivalent to (rcpe to rfpf).
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
Documentation/arm64/silicon-errata.rst | 4 ++++
arch/arm64/kernel/cpu_errata.c | 19 +++++++++++++------
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
index 936cf2a59ca4..f3c0c4393e7e 100644
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -147,6 +147,10 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| Qualcomm Tech. | Falkor v{1,2} | E1041 | QCOM_FALKOR_ERRATUM_1041 |
+----------------+-----------------+-----------------+-----------------------------+
+| Qualcomm Tech. | Kryo4xx Gold | N/A | ARM64_ERRATUM_1463225 |
++----------------+-----------------+-----------------+-----------------------------+
+| Qualcomm Tech. | Kryo4xx Gold | N/A | ARM64_ERRATUM_1418040 |
++----------------+-----------------+-----------------+-----------------------------+
+----------------+-----------------+-----------------+-----------------------------+
| Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
+----------------+-----------------+-----------------+-----------------------------+
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index cf50c53e9357..044f1d7aebdf 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -472,12 +472,7 @@ static bool
has_cortex_a76_erratum_1463225(const struct arm64_cpu_capabilities *entry,
int scope)
{
- u32 midr = read_cpuid_id();
- /* Cortex-A76 r0p0 - r3p1 */
- struct midr_range range = MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1);
-
- WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
- return is_midr_in_range(midr, &range) && is_kernel_in_hyp_mode();
+ return is_affected_midr_range_list(entry, scope) && is_kernel_in_hyp_mode();
}
#endif
@@ -728,6 +723,8 @@ static const struct midr_range erratum_1418040_list[] = {
MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
/* Neoverse-N1 r0p0 to r3p1 */
MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 3, 1),
+ /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
+ MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
{},
};
#endif
@@ -777,6 +774,15 @@ static const struct midr_range erratum_speculative_at_list[] = {
};
#endif
+#ifdef CONFIG_ARM64_ERRATUM_1463225
+static const struct midr_range erratum_1463225[] = {
+ /* Cortex-A76 r0p0 - r3p1 */
+ MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 3, 1),
+ /* Kryo4xx Gold (rcpe to rfpf) => (r0p0 to r3p1) */
+ MIDR_RANGE(MIDR_QCOM_KRYO_4XX_GOLD, 0xc, 0xe, 0xf, 0xf),
+};
+#endif
+
const struct arm64_cpu_capabilities arm64_errata[] = {
#ifdef CONFIG_ARM64_WORKAROUND_CLEAN_CACHE
{
@@ -916,6 +922,7 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
.capability = ARM64_WORKAROUND_1463225,
.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
.matches = has_cortex_a76_erratum_1463225,
+ .midr_range_list = erratum_1463225,
},
#endif
#ifdef CONFIG_CAVIUM_TX2_ERRATUM_219
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread* [PATCH 3/3] arm64: Add KRYO4XX silver CPU cores to erratum list 1530923 and 1024718
2020-06-30 18:00 [PATCH 0/3] Add Kryo4xx gold and silver cores to applicable errata list Sai Prakash Ranjan
2020-06-30 18:00 ` [PATCH 1/3] arm64: Add MIDR value for KRYO4XX gold CPU cores Sai Prakash Ranjan
2020-06-30 18:00 ` [PATCH 2/3] arm64: Add KRYO4XX gold CPU cores to erratum list 1463225 and 1418040 Sai Prakash Ranjan
@ 2020-06-30 18:00 ` Sai Prakash Ranjan
2020-07-03 13:55 ` Will Deacon
2020-07-03 16:35 ` [PATCH 0/3] Add Kryo4xx gold and silver cores to applicable errata list Will Deacon
3 siblings, 1 reply; 6+ messages in thread
From: Sai Prakash Ranjan @ 2020-06-30 18:00 UTC (permalink / raw)
To: Will Deacon, Catalin Marinas, Marc Zyngier, Suzuki K Poulose,
Mark Rutland, Douglas Anderson, Stephen Boyd
Cc: Sai Prakash Ranjan, Jeffrey Hugo, Andre Przywara, linux-kernel,
linux-arm-msm, linux-arm-kernel
KRYO4XX silver/LITTLE CPU cores with revision r1p0 are affected by
erratum 1530923 and 1024718, so add them to the respective list.
The variant and revision bits are implementation defined and are
different from the their Cortex CPU counterparts on which they are
based on, i.e., r1p0 is equivalent to rdpe.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
Documentation/arm64/silicon-errata.rst | 4 ++++
arch/arm64/kernel/cpu_errata.c | 2 ++
arch/arm64/kernel/cpufeature.c | 2 ++
3 files changed, 8 insertions(+)
diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
index f3c0c4393e7e..3f7c3a7e8a2b 100644
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -151,6 +151,10 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| Qualcomm Tech. | Kryo4xx Gold | N/A | ARM64_ERRATUM_1418040 |
+----------------+-----------------+-----------------+-----------------------------+
+| Qualcomm Tech. | Kryo4xx Silver | N/A | ARM64_ERRATUM_1530923 |
++----------------+-----------------+-----------------+-----------------------------+
+| Qualcomm Tech. | Kryo4xx Silver | N/A | ARM64_ERRATUM_1024718 |
++----------------+-----------------+-----------------+-----------------------------+
+----------------+-----------------+-----------------+-----------------------------+
| Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
+----------------+-----------------+-----------------+-----------------------------+
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 044f1d7aebdf..8e302dc093d0 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -769,6 +769,8 @@ static const struct midr_range erratum_speculative_at_list[] = {
#ifdef CONFIG_ARM64_ERRATUM_1530923
/* Cortex A55 r0p0 to r2p0 */
MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 2, 0),
+ /* Kryo4xx Silver (rdpe => r1p0) */
+ MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
#endif
{},
};
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 9f63053a63a9..9fae0efc80c1 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -1408,6 +1408,8 @@ static bool cpu_has_broken_dbm(void)
static const struct midr_range cpus[] = {
#ifdef CONFIG_ARM64_ERRATUM_1024718
MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0), // A55 r0p0 -r1p0
+ /* Kryo4xx Silver (rdpe => r1p0) */
+ MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
#endif
{},
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH 3/3] arm64: Add KRYO4XX silver CPU cores to erratum list 1530923 and 1024718
2020-06-30 18:00 ` [PATCH 3/3] arm64: Add KRYO4XX silver CPU cores to erratum list 1530923 and 1024718 Sai Prakash Ranjan
@ 2020-07-03 13:55 ` Will Deacon
0 siblings, 0 replies; 6+ messages in thread
From: Will Deacon @ 2020-07-03 13:55 UTC (permalink / raw)
To: Sai Prakash Ranjan
Cc: Mark Rutland, Suzuki K Poulose, Jeffrey Hugo, Catalin Marinas,
linux-arm-msm, Douglas Anderson, Stephen Boyd, Andre Przywara,
linux-arm-kernel, Marc Zyngier, linux-kernel
On Tue, Jun 30, 2020 at 11:30:55PM +0530, Sai Prakash Ranjan wrote:
> KRYO4XX silver/LITTLE CPU cores with revision r1p0 are affected by
> erratum 1530923 and 1024718, so add them to the respective list.
> The variant and revision bits are implementation defined and are
> different from the their Cortex CPU counterparts on which they are
> based on, i.e., r1p0 is equivalent to rdpe.
So just to confirm, revisions prior to rdpe are unaffected, or do those
parts simply not exist?
Cheers,
Will
_______________________________________________
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/3] Add Kryo4xx gold and silver cores to applicable errata list
2020-06-30 18:00 [PATCH 0/3] Add Kryo4xx gold and silver cores to applicable errata list Sai Prakash Ranjan
` (2 preceding siblings ...)
2020-06-30 18:00 ` [PATCH 3/3] arm64: Add KRYO4XX silver CPU cores to erratum list 1530923 and 1024718 Sai Prakash Ranjan
@ 2020-07-03 16:35 ` Will Deacon
3 siblings, 0 replies; 6+ messages in thread
From: Will Deacon @ 2020-07-03 16:35 UTC (permalink / raw)
To: Stephen Boyd, Sai Prakash Ranjan, Douglas Anderson,
Suzuki K Poulose, Marc Zyngier, Catalin Marinas, Mark Rutland
Cc: kernel-team, Jeffrey Hugo, linux-arm-msm, linux-kernel,
Andre Przywara, Will Deacon, linux-arm-kernel
On Tue, 30 Jun 2020 23:30:52 +0530, Sai Prakash Ranjan wrote:
> This series adds the Kryo4xx gold/big and silver/LITTLE CPU cores to
> the errata list which are applicable to them based on the revisions
> of the Cortex CPU cores on which they are based on.
>
> Patch 1 adds the MIDR value for Kryo4xx gold CPU cores.
> Patch 2 adds Kryo4xx gold CPU cores to erratum list 1463225 and 1418040.
> Patch 3 adds Kryo4xx silver CPU cores to erratum list 1530923 and 1024718.
>
> [...]
Applied to arm64 (for-next/fixes), thanks!
[1/3] arm64: Add MIDR value for KRYO4XX gold CPU cores
https://git.kernel.org/arm64/c/dce4f2807f69
[2/3] arm64: Add KRYO4XX gold CPU cores to erratum list 1463225 and 1418040
https://git.kernel.org/arm64/c/a9e821b89daa
[3/3] arm64: Add KRYO4XX silver CPU cores to erratum list 1530923 and 1024718
https://git.kernel.org/arm64/c/9b23d95c539e
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
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^ permalink raw reply [flat|nested] 6+ messages in thread