From: icenowy@aosc.io (icenowy at aosc.io)
To: linux-arm-kernel@lists.infradead.org
Subject: [linux-sunxi] Re: [RFC PATCH 07/11] drm: sun4i: add support for the TV encoder in H3 SoC
Date: Sun, 04 Jun 2017 22:29:29 +0800 [thread overview]
Message-ID: <861ead704cc7d1bc0983d0f01138f190@aosc.io> (raw)
In-Reply-To: <20170524073019.bl6rojc2srrigalp@flea.home>
? 2017-05-24 15:30?Maxime Ripard ???
> On Tue, May 23, 2017 at 09:00:59PM +0800, icenowy at aosc.io wrote:
>> ? 2017-05-23 20:53?Maxime Ripard ???
>> > On Mon, May 22, 2017 at 07:55:56PM +0200, Jernej ?krabec wrote:
>> > > Hi,
>> > >
>> > > Dne sobota, 20. maj 2017 ob 03:37:53 CEST je Chen-Yu Tsai napisal(a):
>> > > > On Sat, May 20, 2017 at 2:23 AM, Jernej ?krabec <jernej.skrabec@siol.net>
>> > > wrote:
>> > > > > Hi,
>> > > > >
>> > > > > Dne petek, 19. maj 2017 ob 20:08:18 CEST je Icenowy Zheng napisal(a):
>> > > > >> ? 2017?5?20? GMT+08:00 ??2:03:30, Maxime Ripard <maxime.ripard@free-
>> > > > >
>> > > > > electrons.com> ??:
>> > > > >> >On Thu, May 18, 2017 at 12:43:50AM +0800, Icenowy Zheng wrote:
>> > > > >> >> Allwinner H3 features a TV encoder similar to the one in earlier
>> > > > >> >
>> > > > >> >SoCs,
>> > > > >> >
>> > > > >> >> but with some different points about clocks:
>> > > > >> >> - It has a mod clock and a bus clock.
>> > > > >> >> - The mod clock must be at a fixed rate to generate signal.
>> > > > >> >
>> > > > >> >Why?
>> > > > >>
>> > > > >> It's experiment result by Jernej.
>> > > > >>
>> > > > >> The clock rates in BSP kernel is also specially designed
>> > > > >> (PLL_DE at 432MHz) in order to be able to feed the TVE.
>> > > > >
>> > > > > My experiments and search through BSP code showed that TVE seems to have
>> > > > > additional fixed predivider 8. So if you want to generate 27 MHz clock,
>> > > > > unit has to be feed with 216 MHz.
>> > > > >
>> > > > > TVE has only one PLL source PLL_DE. And since 216 MHz is a bit low for
>> > > > > DE2,
>> > > > > BSP defaults to 432 MHz for PLL_DE and use divider 2 to generate 216 MHz.
>> > > > > This clock is then divided by 8 internaly to get final 27 MHz.
>> > > > >
>> > > > > Please note that I don't have any hard evidence to support that, only
>> > > > > experimental data. However, only that explanation make sense to me.
>> > > > >
>> > > > > BTW, BSP H3/H5 TV driver supports only PAL and NTSC which both use 27 MHz
>> > > > > base clock. Further experiments are needed to check if there is any
>> > > > > possibility to have other resolutions by manipulating clocks and give
>> > > > > other proper settings. I plan to do that, but not in very near future.
>> > > >
>> > > > You only have composite video output, and those are the only 2 standard
>> > > > resolutions that make any sense.
>> > >
>> > > Right, other resolutions are for VGA.
>> > >
>> > > Anyway, I did some more digging in A10 and R40 datasheets. I think
>> > > that H3 TVE
>> > > unit is something in between. R40 TVE has a setting to select "up
>> > > sample".
>> >
>> > That might be just another translation of oversampling :)
>> >
>> > I didn't know it could be applied to composite signals though, but I
>> > guess this is just another analog signal after all.
>> >
>> > > Possible settings are 27 MHz, 54 MHz, 108 MHz and 216 MHz. BSP
>> > > driver on R40
>> > > has this setting enabled only for PAL and NTSC and it is always 216
>> > > MHz. I
>> > > think that H3 may have this hardwired to 216 MHz and this would be
>> > > the reason
>> > > why 216 MHz is needed.
>> > >
>> > > Has anyone else any better explanation?
>> >
>> > That's already a pretty good one.
>> >
>> > Either way, wether this is upsampling, oversampling or just a
>> > pre-divider, this can and should be dealt with in the mode_set
>> > callback, and not in the probe.
>>
>> I got a better idea -- let TVE driver have the CLK_TVE as an
>> input and create a subclock output with divider 16, and feed this
>> subclock to TCON lcd-ch1.
>>
>> This is a model of the real hardware -- the clock divider is in
>> TVE, not TCON.
>
> That's definitely not a good representation of the hardware. There's
> one clock, it goes to the TCON, period.
>
> However, the TV encoder has a constraint on that clock rate. This can
> be easily implemented using a custom encoder state where you'd set the
> multiplier to set on that clock, and the TCON will use it.
P.S. how to do such a custom state?
Should I do the multiplying in sun4i_tv_mode_to_drm_mode?
>
> Maxime
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2017-06-04 14:29 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-17 16:43 [RFC PATCH 00/11] Support for H3 Composite Output support Icenowy Zheng
2017-05-17 16:43 ` [RFC PATCH 01/11] dt-bindings: update the binding for Allwinner H3 TVE support Icenowy Zheng
2017-05-19 18:02 ` Maxime Ripard
2017-05-19 18:06 ` Icenowy Zheng
2017-05-20 2:01 ` [linux-sunxi] " Chen-Yu Tsai
2017-05-17 16:43 ` [RFC PATCH 02/11] drm: sun4i: add support for H3 mixers Icenowy Zheng
2017-05-19 17:47 ` Maxime Ripard
2017-05-19 17:49 ` [linux-sunxi] " Icenowy Zheng
2017-05-19 18:00 ` Jernej Škrabec
2017-05-17 16:43 ` [RFC PATCH 03/11] drm: sun4i: ignore swapped mixer<->tcon connection for DE2 Icenowy Zheng
2017-05-19 17:57 ` Maxime Ripard
2017-05-19 18:00 ` Icenowy Zheng
2017-05-24 8:14 ` Maxime Ripard
2017-06-04 14:19 ` icenowy at aosc.io
2017-05-17 16:43 ` [RFC PATCH 04/11] drm: sun4i: add support for H3's TCON0/1 Icenowy Zheng
2017-05-17 16:43 ` [RFC PATCH 05/11] drm: sun4i: add compatible for H3 display engine Icenowy Zheng
2017-05-17 16:43 ` [RFC PATCH 06/11] drm: sun4i: add color space correction support for DE2 mixer Icenowy Zheng
2017-05-17 20:14 ` [linux-sunxi] " Jernej Škrabec
2017-05-17 16:43 ` [RFC PATCH 07/11] drm: sun4i: add support for the TV encoder in H3 SoC Icenowy Zheng
2017-05-19 18:03 ` Maxime Ripard
2017-05-19 18:08 ` Icenowy Zheng
2017-05-19 18:23 ` [linux-sunxi] " Jernej Škrabec
2017-05-20 1:37 ` Chen-Yu Tsai
2017-05-22 17:55 ` Jernej Škrabec
2017-05-23 12:53 ` Maxime Ripard
2017-05-23 12:56 ` Icenowy Zheng
2017-05-23 13:00 ` icenowy at aosc.io
2017-05-24 7:30 ` Maxime Ripard
2017-05-24 8:25 ` Icenowy Zheng
2017-05-24 15:23 ` Jernej Škrabec
2017-05-31 18:43 ` Maxime Ripard
2017-06-01 14:11 ` icenowy at aosc.io
2017-06-02 22:21 ` Maxime Ripard
2017-06-04 14:29 ` icenowy at aosc.io [this message]
2017-06-07 7:58 ` Maxime Ripard
2017-05-17 16:43 ` [RFC PATCH 08/11] clk: sunxi-ng: allow CLK_DE to set CLK_PLL_DE for H3 Icenowy Zheng
2017-05-17 16:43 ` [RFC PATCH 09/11] clk: sunxi-ng: export " Icenowy Zheng
2017-05-17 16:43 ` [RFC PATCH 10/11] ARM: sun8i: h3: add display engine pipeline for TVE Icenowy Zheng
2017-05-17 20:19 ` [linux-sunxi] " Jernej Škrabec
2017-05-19 18:06 ` Maxime Ripard
2017-05-19 18:10 ` [linux-sunxi] " Icenowy Zheng
2017-05-24 8:19 ` Maxime Ripard
2017-05-24 5:24 ` [linux-sunxi] " Chen-Yu Tsai
2017-05-24 5:28 ` Icenowy Zheng
2017-05-24 5:34 ` Chen-Yu Tsai
2017-05-24 5:36 ` Icenowy Zheng
2017-05-17 16:43 ` [RFC PATCH 11/11] [DO NOT MERGE] ARM: sun8i: h3: enable TV output on Orange Pi PC Icenowy Zheng
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