[PATCH RFC 14/18] HACK: pinctrl: bcm2835: Implement legacy pull for BCM7211

[PATCH RFC 14/18] HACK: pinctrl: bcm2835: Implement legacy pull for BCM7211

[Stefan Wahren]

This temporay hack is necessary to make the BCM2838/7211 work with the legacy
pull configuration. The better approach is to convert all affected DTS files
to the generic bias control.

Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
---
 drivers/pinctrl/bcm/pinctrl-bcm2835.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
index 7f7cc5c..56161b6 100644
--- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
@@ -1003,6 +1003,13 @@ static int bcm7211_pinconf_set(struct pinctrl_dev *pctldev,

 		/* convert to 7211 value */
 		switch (param) {
+		case BCM2835_PINCONF_PARAM_PULL:
+			/* convert legacy brcm,pull */
+			if (arg == BCM2835_PUD_UP)
+				arg = BCM7211_PINCONFIG_PULL_UP;
+			else if (arg == BCM2835_PUD_DOWN)
+				arg = BCM7211_PINCONFIG_PULL_DOWN;
+			break;
 		case PIN_CONFIG_BIAS_DISABLE:
 			arg = BCM7211_PINCONFIG_PULL_NONE;
 			break;
--
2.7.4


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[PATCH RFC 15/18] spi: bcm2835: enable shared interrupt support

[Stefan Wahren]

From: Martin Sperl <kernel@martin.sperl.org>

The new BCM2838 share one interrupt for multiple instances of the BCM2835
SPI controller. So this enables shared interrupt support for them.

Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
---
 drivers/spi/spi-bcm2835.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-bcm2835.c b/drivers/spi/spi-bcm2835.c
index 6f243a9..50969ae 100644
--- a/drivers/spi/spi-bcm2835.c
+++ b/drivers/spi/spi-bcm2835.c
@@ -346,6 +346,10 @@ static irqreturn_t bcm2835_spi_interrupt(int irq, void *dev_id)
 	if (bs->tx_len && cs & BCM2835_SPI_CS_DONE)
 		bcm2835_wr_fifo_blind(bs, BCM2835_SPI_FIFO_SIZE);

+	/* check if we got interrupt enabled */
+	if (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_INTR))
+		return IRQ_NONE;
+
 	/* Read as many bytes as possible from FIFO */
 	bcm2835_rd_fifo(bs);
 	/* Write as many bytes as possible to FIFO */
@@ -1028,8 +1032,8 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
 	bcm2835_wr(bs, BCM2835_SPI_CS,
 		   BCM2835_SPI_CS_CLEAR_RX | BCM2835_SPI_CS_CLEAR_TX);

-	err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt, 0,
-			       dev_name(&pdev->dev), ctlr);
+	err = devm_request_irq(&pdev->dev, bs->irq, bcm2835_spi_interrupt,
+			       IRQF_SHARED, dev_name(&pdev->dev), ctlr);
 	if (err) {
 		dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
 		goto out_clk_disable;
--
2.7.4


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[PATCH RFC 16/18] dt-bindings: bcm: Add Raspberry Pi 4 B

[Stefan Wahren]

This adds the root properties for the Raspberry Pi 4 B.

Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
---
 Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
index 245328f..d031e10 100644
--- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm2835.txt
@@ -54,6 +54,10 @@ Raspberry Pi Compute Module 3 Lite
 Required root node properties:
 compatible = "raspberrypi,3-compute-module-lite", "brcm,bcm2837";

+Raspberry Pi 4 Model B
+Required root node properties:
+compatible = "raspberrypi,4-model-b", "brcm,bcm2838";
+
 Raspberry Pi Zero
 Required root node properties:
 compatible = "raspberrypi,model-zero", "brcm,bcm2835";
--
2.7.4


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[PATCH RFC 17/18] ARM: bcm2835: Add bcm2838 compatible string

[Stefan Wahren]

From: Phil Elwell <phil@raspberrypi.org>

This adds support for the new BCM2838 SoC found on the Raspberry Pi 4.

Signed-off-by: Phil Elwell <phil@raspberrypi.org>
---
 arch/arm/mach-bcm/board_bcm2835.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-bcm/board_bcm2835.c b/arch/arm/mach-bcm/board_bcm2835.c
index d2b31a9..578eaaa 100644
--- a/arch/arm/mach-bcm/board_bcm2835.c
+++ b/arch/arm/mach-bcm/board_bcm2835.c
@@ -19,6 +19,7 @@ static const char * const bcm2835_compat[] = {
 #ifdef CONFIG_ARCH_MULTI_V7
 	"brcm,bcm2836",
 	"brcm,bcm2837",
+	"brcm,bcm2838",
 #endif
 	NULL
 };
--
2.7.4


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[PATCH RFC 18/18] ARM: dts: Add minimal Raspberry Pi 4 support

[Stefan Wahren]

This adds minimal support for the new Raspberry Pi 4 without the
fancy stuff like GENET, PCIe, XHCI, 40 bit DMA and V3D. The RPi 4 is available
in 3 different variants (1, 2 and 4 GB RAM), so leave the memory size to zero
and let the bootloader take care of it.

Other differences to the Raspberry Pi 3:
- additional GIC 400 Interrupt controller
- new thermal IP and HWRNG
- additional MMC interface (emmc2)
- additional UART, I2C, SPI and PWM interfaces

Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
---
 arch/arm/boot/dts/Makefile            |   1 +
 arch/arm/boot/dts/bcm2838-rpi-4-b.dts | 120 +++++++
 arch/arm/boot/dts/bcm2838.dtsi        | 657 ++++++++++++++++++++++++++++++++++
 arch/arm/boot/dts/bcm283x.dtsi        |   2 +-
 4 files changed, 779 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/bcm2838-rpi-4-b.dts
 create mode 100644 arch/arm/boot/dts/bcm2838.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9159fa2..7ec9c90 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -83,6 +83,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \
 	bcm2837-rpi-3-b.dtb \
 	bcm2837-rpi-3-b-plus.dtb \
 	bcm2837-rpi-cm3-io3.dtb \
+	bcm2838-rpi-4-b.dtb \
 	bcm2835-rpi-zero.dtb \
 	bcm2835-rpi-zero-w.dtb
 dtb-$(CONFIG_ARCH_BCM_5301X) += \
diff --git a/arch/arm/boot/dts/bcm2838-rpi-4-b.dts b/arch/arm/boot/dts/bcm2838-rpi-4-b.dts
new file mode 100644
index 0000000..38308d4
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2838-rpi-4-b.dts
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+#include "bcm2838.dtsi"
+#include "bcm2835-rpi.dtsi"
+
+/ {
+	compatible = "raspberrypi,4-model-b", "brcm,bcm2838";
+	model = "Raspberry Pi 4 Model B";
+
+	chosen {
+		/* 8250 auxiliary UART instead of pl011 */
+		stdout-path = "serial1:115200n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0 0 0x00000000>;
+	};
+
+	leds {
+		act {
+			gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
+		};
+
+		pwr {
+			label = "PWR";
+			gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	wifi_pwrseq: wifi-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
+	};
+
+	sd_io_1v8_reg: sd_io_1v8_reg {
+		compatible = "regulator-gpio";
+		regulator-name = "vdd-sd-io";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+		regulator-settling-time-us = <5000>;
+		gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>;
+		states = <1800000 0x1
+			  3300000 0x0>;
+		status = "okay";
+	};
+};
+
+&firmware {
+	expgpio: gpio {
+		compatible = "raspberrypi,firmware-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+		gpio-line-names = "BT_ON",
+				  "WL_ON",
+				  "PWR_LED_OFF",
+				  "GLOBAL_RESET",
+				  "VDD_SD_IO_SEL",
+				  "CAM_GPIO",
+				  "",
+				  "";
+		status = "okay";
+	};
+};
+
+&pwm1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>;
+	status = "okay";
+};
+
+/* SDHCI is used to control the SDIO for wireless */
+&sdhci {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_gpio34>;
+	bus-width = <4>;
+	non-removable;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	status = "okay";
+
+	brcmf: wifi@1 {
+		reg = <1>;
+		compatible = "brcm,bcm4329-fmac";
+	};
+};
+
+/* EMMC2 is used to drive the SD card */
+&emmc2 {
+	vqmmc-supply = <&sd_io_1v8_reg>;
+	broken-cd;
+	status = "okay";
+};
+
+/* uart0 communicates with the BT module */
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32 &gpclk2_gpio43>;
+	status = "okay";
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		max-speed = <2000000>;
+		shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+/* uart1 is mapped to the pin header */
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_gpio14>;
+	status = "okay";
+};
+
+&vchiq {
+	interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/arch/arm/boot/dts/bcm2838.dtsi b/arch/arm/boot/dts/bcm2838.dtsi
new file mode 100644
index 0000000..e004d70
--- /dev/null
+++ b/arch/arm/boot/dts/bcm2838.dtsi
@@ -0,0 +1,657 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "bcm283x.dtsi"
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/soc/bcm2835-pm.h>
+
+/ {
+	compatible = "brcm,bcm2838";
+
+	#address-cells = <2>;
+	#size-cells = <1>;
+
+	interrupt-parent = <&gicv2>;
+
+	soc {
+		ranges = <0x7e000000  0x0 0xfe000000  0x01800000>,
+			 <0x7c000000  0x0 0xfc000000  0x02000000>,
+			 <0x40000000  0x0 0xff800000  0x00800000>;
+		/* Emulate a contiguous 30-bit address range for DMA */
+		dma-ranges = <0xc0000000  0x0 0x00000000  0x3c000000>;
+
+		local_intc: local_intc@40000000 {
+			compatible = "brcm,bcm2836-l1-intc";
+			reg = <0x40000000 0x100>;
+		};
+
+		gicv2: gic400@40041000 {
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			compatible = "arm,gic-400";
+			reg =	<0x40041000 0x1000>,
+				<0x40042000 0x2000>,
+				<0x40044000 0x2000>,
+				<0x40046000 0x2000>;
+		};
+
+		dma: dma@7e007000 {
+			compatible = "brcm,bcm2835-dma";
+			reg = <0x7e007000 0xb00>;
+			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, /* dmalite  7 */
+				     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, /* dmalite  8 */
+				     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, /* dmalite  9 */
+				     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; /* dmalite 10 */
+			interrupt-names = "dma0",
+					  "dma1",
+					  "dma2",
+					  "dma3",
+					  "dma4",
+					  "dma5",
+					  "dma6",
+					  "dma7",
+					  "dma8",
+					  "dma9",
+					  "dma10";
+			#dma-cells = <1>;
+			brcm,dma-channel-mask = <0x07f5>;
+		};
+
+		pm: watchdog@7e100000 {
+			reg = <0x7e100000 0x114>,
+			      <0x7e00a000 0x24>,
+			      <0x7ec11000 0x20>;
+		};
+
+		rng@7e104000 {
+			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+
+			/* RNG is incompatible to brcm,bcm2835-rng */
+			status = "disabled";
+		};
+
+		uart2: serial@7e201400 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x7e201400 0x200>;
+			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clocks BCM2835_CLOCK_UART>,
+				 <&clocks BCM2835_CLOCK_VPU>;
+			clock-names = "uartclk", "apb_pclk";
+			arm,primecell-periphid = <0x00241011>;
+			status = "disabled";
+		};
+
+		uart3: serial@7e201600 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x7e201600 0x200>;
+			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clocks BCM2835_CLOCK_UART>,
+				 <&clocks BCM2835_CLOCK_VPU>;
+			clock-names = "uartclk", "apb_pclk";
+			arm,primecell-periphid = <0x00241011>;
+			status = "disabled";
+		};
+
+		uart4: serial@7e201800 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x7e201800 0x200>;
+			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clocks BCM2835_CLOCK_UART>,
+				 <&clocks BCM2835_CLOCK_VPU>;
+			clock-names = "uartclk", "apb_pclk";
+			arm,primecell-periphid = <0x00241011>;
+			status = "disabled";
+		};
+
+		uart5: serial@7e201a00 {
+			compatible = "arm,pl011", "arm,primecell";
+			reg = <0x7e201a00 0x200>;
+			interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clocks BCM2835_CLOCK_UART>,
+				 <&clocks BCM2835_CLOCK_VPU>;
+			clock-names = "uartclk", "apb_pclk";
+			arm,primecell-periphid = <0x00241011>;
+			status = "disabled";
+		};
+
+		spi@7e204000 {
+			reg = <0x7e204000 0x0200>;
+			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		spi3: spi@7e204600 {
+			compatible = "brcm,bcm2835-spi";
+			reg = <0x7e204600 0x0200>;
+			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clocks BCM2835_CLOCK_VPU>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi4: spi@7e204800 {
+			compatible = "brcm,bcm2835-spi";
+			reg = <0x7e204800 0x0200>;
+			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clocks BCM2835_CLOCK_VPU>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi5: spi@7e204a00 {
+			compatible = "brcm,bcm2835-spi";
+			reg = <0x7e204a00 0x0200>;
+			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clocks BCM2835_CLOCK_VPU>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi6: spi@7e204c00 {
+			compatible = "brcm,bcm2835-spi";
+			reg = <0x7e204c00 0x0200>;
+			interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clocks BCM2835_CLOCK_VPU>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@7e205600 {
+			compatible = "brcm,bcm2835-i2c";
+			reg = <0x7e205600 0x200>;
+			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clocks BCM2835_CLOCK_VPU>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@7e205800 {
+			compatible = "brcm,bcm2835-i2c";
+			reg = <0x7e205800 0x200>;
+			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clocks BCM2835_CLOCK_VPU>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c5: i2c@7e205a00 {
+			compatible = "brcm,bcm2835-i2c";
+			reg = <0x7e205a00 0x200>;
+			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clocks BCM2835_CLOCK_VPU>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c6: i2c@7e205c00 {
+			compatible = "brcm,bcm2835-i2c";
+			reg = <0x7e205c00 0x200>;
+			interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clocks BCM2835_CLOCK_VPU>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		pixelvalve@7e206000 {
+			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pixelvalve@7e207000 {
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pwm1: pwm@7e20c800 {
+			compatible = "brcm,bcm2835-pwm";
+			reg = <0x7e20c800 0x28>;
+			clocks = <&clocks BCM2835_CLOCK_PWM>;
+			assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
+			assigned-clock-rates = <10000000>;
+			#pwm-cells = <2>;
+			status = "disabled";
+		};
+
+		emmc2: emmc2@7e340000 {
+			compatible = "brcm,bcm2838-emmc2";
+			reg = <0x7e340000 0x100>;
+			interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clocks BCM2838_CLOCK_EMMC2>;
+			status = "disabled";
+		};
+
+		hvs@7e400000 {
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pixelvalve@7e807000 {
+			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+		};
+	};
+
+	arm-pmu {
+		/*
+		 * N.B. the A72 PMU support only exists in arch/arm64, hence
+		 * the fallback to the A53 version.
+		 */
+		compatible = "arm,cortex-a72-pmu", "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
+					  IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
+					  IRQ_TYPE_LEVEL_LOW)>;
+		arm,cpu-registers-not-fw-configured;
+		always-on;
+	};
+
+	cpus: cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <0>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x000000d8>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <1>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x000000e0>;
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <2>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x000000e8>;
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a72";
+			reg = <3>;
+			enable-method = "spin-table";
+			cpu-release-addr = <0x0 0x000000f0>;
+		};
+	};
+};
+
+&clk_osc {
+	clock-frequency = <54000000>;
+};
+
+&clocks {
+	compatible = "brcm,bcm2838-cprman";
+};
+
+&cpu_thermal {
+	coefficients = <(-487) 410040>;
+};
+
+&dsi0 {
+	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&dsi1 {
+	interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&gpio {
+	compatible = "brcm,bcm2838-gpio";
+	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+
+	gpclk0_gpio49: gpclk0_gpio49 {
+		brcm,pins = <49>;
+		brcm,function = <BCM2835_FSEL_ALT1>;
+		bias-disable;
+	};
+	gpclk1_gpio50: gpclk1_gpio50 {
+		brcm,pins = <50>;
+		brcm,function = <BCM2835_FSEL_ALT1>;
+		bias-disable;
+	};
+	gpclk2_gpio51: gpclk2_gpio51 {
+		brcm,pins = <51>;
+		brcm,function = <BCM2835_FSEL_ALT1>;
+		bias-disable;
+	};
+
+	i2c0_gpio46: i2c0_gpio46 {
+		brcm,pins = <46 47>;
+		brcm,function = <BCM2835_FSEL_ALT0>;
+	};
+	i2c1_gpio46: i2c1_gpio46 {
+		brcm,pins = <46 47>;
+		brcm,function = <BCM2835_FSEL_ALT1>;
+	};
+	i2c3_gpio2: i2c3_gpio2 {
+		brcm,pins = <2 3>;
+		brcm,function = <BCM2835_FSEL_ALT5>;
+	};
+	i2c3_gpio4: i2c3_gpio4 {
+		brcm,pins = <4 5>;
+		brcm,function = <BCM2835_FSEL_ALT5>;
+	};
+	i2c4_gpio6: i2c4_gpio6 {
+		brcm,pins = <6 7>;
+		brcm,function = <BCM2835_FSEL_ALT5>;
+	};
+	i2c4_gpio8: i2c4_gpio8 {
+		brcm,pins = <8 9>;
+		brcm,function = <BCM2835_FSEL_ALT5>;
+	};
+	i2c5_gpio10: i2c5_gpio10 {
+		brcm,pins = <10 11>;
+		brcm,function = <BCM2835_FSEL_ALT5>;
+	};
+	i2c5_gpio12: i2c5_gpio12 {
+		brcm,pins = <12 13>;
+		brcm,function = <BCM2835_FSEL_ALT5>;
+	};
+	i2c6_gpio0: i2c6_gpio0 {
+		brcm,pins = <0 1>;
+		brcm,function = <BCM2835_FSEL_ALT5>;
+	};
+	i2c6_gpio22: i2c6_gpio22 {
+		brcm,pins = <22 23>;
+		brcm,function = <BCM2835_FSEL_ALT5>;
+	};
+	i2c_slave_gpio8: i2c_slave_gpio8 {
+		brcm,pins = <8 9 10 11>;
+		brcm,function = <BCM2835_FSEL_ALT3>;
+	};
+
+	jtag_gpio48: jtag_gpio48 {
+		brcm,pins = <48 49 50 51 52 53>;
+		brcm,function = <BCM2835_FSEL_ALT4>;
+	};
+
+	mii_gpio28: mii_gpio28 {
+		brcm,pins = <28 29 30 31>;
+		brcm,function = <BCM2835_FSEL_ALT4>;
+	};
+	mii_gpio36: mii_gpio36 {
+		brcm,pins = <36 37 38 39>;
+		brcm,function = <BCM2835_FSEL_ALT5>;
+	};
+
+	pcm_gpio50: pcm_gpio50 {
+		brcm,pins = <50 51 52 53>;
+		brcm,function = <BCM2835_FSEL_ALT2>;
+	};
+
+	pwm0_0_gpio12: pwm0_0_gpio12 {
+		brcm,pins = <12>;
+		brcm,function = <BCM2835_FSEL_ALT0>;
+	};
+	pwm0_0_gpio18: pwm0_0_gpio18 {
+		brcm,pins = <18>;
+		brcm,function = <BCM2835_FSEL_ALT5>;
+	};
+	pwm1_0_gpio40: pwm1_0_gpio40 {
+		brcm,pins = <40>;
+		brcm,function = <BCM2835_FSEL_ALT0>;
+	};
+	pwm0_1_gpio13: pwm0_1_gpio13 {
+		brcm,pins = <13>;
+		brcm,function = <BCM2835_FSEL_ALT0>;
+	};
+	pwm0_1_gpio19: pwm0_1_gpio19 {
+		brcm,pins = <19>;
+		brcm,function = <BCM2835_FSEL_ALT5>;
+	};
+	pwm1_1_gpio41: pwm1_1_gpio41 {
+		brcm,pins = <41>;
+		brcm,function = <BCM2835_FSEL_ALT0>;
+	};
+	pwm0_1_gpio45: pwm0_1_gpio45 {
+		brcm,pins = <45>;
+		brcm,function = <BCM2835_FSEL_ALT0>;
+	};
+	pwm0_0_gpio52: pwm0_0_gpio52 {
+		brcm,pins = <52>;
+		brcm,function = <BCM2835_FSEL_ALT1>;
+		bias-disable;
+	};
+	pwm0_1_gpio53: pwm0_1_gpio53 {
+		brcm,pins = <53>;
+		brcm,function = <BCM2835_FSEL_ALT1>;
+		bias-disable;
+	};
+
+	/* The following group consists of:
+	 *  RGMII_START_STOP
+	 *  RGMII_RX_OK
+	 */
+	rgmii_gpio35: rgmii_gpio35 {
+		brcm,pins = <35 36>;
+		brcm,function = <BCM2835_FSEL_ALT4>;
+	};
+	rgmii_irq_gpio34: rgmii_irq_gpio34 {
+		brcm,pins = <34>;
+		brcm,function = <BCM2835_FSEL_ALT5>;
+	};
+	rgmii_irq_gpio39: rgmii_irq_gpio39 {
+		brcm,pins = <39>;
+		brcm,function = <BCM2835_FSEL_ALT4>;
+	};
+	rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
+		brcm,pins = <28 29>;
+		brcm,function = <BCM2835_FSEL_ALT5>;
+	};
+	rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
+		brcm,pins = <37 38>;
+		brcm,function = <BCM2835_FSEL_ALT4>;
+	};
+
+	spi0_gpio46: spi0_gpio46 {
+		brcm,pins = <46 47 48 49>;
+		brcm,function = <BCM2835_FSEL_ALT2>;
+	};
+	spi2_gpio46: spi2_gpio46 {
+		brcm,pins = <46 47 48 49 50>;
+		brcm,function = <BCM2835_FSEL_ALT5>;
+	};
+	spi3_gpio0: spi3_gpio0 {
+		brcm,pins = <0 1 2 3>;
+		brcm,function = <BCM2835_FSEL_ALT3>;
+	};
+	spi4_gpio4: spi4_gpio4 {
+		brcm,pins = <4 5 6 7>;
+		brcm,function = <BCM2835_FSEL_ALT3>;
+	};
+	spi5_gpio12: spi5_gpio12 {
+		brcm,pins = <12 13 14 15>;
+		brcm,function = <BCM2835_FSEL_ALT3>;
+	};
+	spi6_gpio18: spi6_gpio18 {
+		brcm,pins = <18 19 20 21>;
+		brcm,function = <BCM2835_FSEL_ALT3>;
+	};
+
+	uart2_gpio0: uart2_gpio0 {
+		pin-tx {
+			brcm,pins = <0>;
+			brcm,function = <BCM2835_FSEL_ALT4>;
+			bias-disable;
+		};
+		pin-rx {
+			brcm,pins = <1>;
+			brcm,function = <BCM2835_FSEL_ALT4>;
+			bias-pull-up;
+		};
+	};
+	uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
+		pin-cts {
+			brcm,pins = <2>;
+			brcm,function = <BCM2835_FSEL_ALT4>;
+			bias-pull-up;
+		};
+		pin-rts {
+			brcm,pins = <3>;
+			brcm,function = <BCM2835_FSEL_ALT4>;
+			bias-disable;
+		};
+	};
+	uart3_gpio4: uart3_gpio4 {
+		pin-tx {
+			brcm,pins = <4>;
+			brcm,function = <BCM2835_FSEL_ALT4>;
+			bias-disable;
+		};
+		pin-rx {
+			brcm,pins = <5>;
+			brcm,function = <BCM2835_FSEL_ALT4>;
+			bias-pull-up;
+		};
+	};
+	uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
+		pin-cts {
+			brcm,pins = <6>;
+			brcm,function = <BCM2835_FSEL_ALT4>;
+			bias-pull-up;
+		};
+		pin-rts {
+			brcm,pins = <7>;
+			brcm,function = <BCM2835_FSEL_ALT4>;
+			bias-disable;
+		};
+	};
+	uart4_gpio8: uart4_gpio8 {
+		pin-tx {
+			brcm,pins = <8>;
+			brcm,function = <BCM2835_FSEL_ALT4>;
+			bias-disable;
+		};
+		pin-rx {
+			brcm,pins = <9>;
+			brcm,function = <BCM2835_FSEL_ALT4>;
+			bias-pull-up;
+		};
+	};
+	uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
+		pin-cts {
+			brcm,pins = <10>;
+			brcm,function = <BCM2835_FSEL_ALT4>;
+			bias-pull-up;
+		};
+		pin-rts {
+			brcm,pins = <11>;
+			brcm,function = <BCM2835_FSEL_ALT4>;
+			bias-disable;
+		};
+	};
+	uart5_gpio12: uart5_gpio12 {
+		pin-tx {
+			brcm,pins = <12>;
+			brcm,function = <BCM2835_FSEL_ALT4>;
+			bias-disable;
+		};
+		pin-rx {
+			brcm,pins = <13>;
+			brcm,function = <BCM2835_FSEL_ALT4>;
+			bias-pull-up;
+		};
+	};
+	uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
+		pin-cts {
+			brcm,pins = <14>;
+			brcm,function = <BCM2835_FSEL_ALT4>;
+			bias-pull-up;
+		};
+		pin-rts {
+			brcm,pins = <15>;
+			brcm,function = <BCM2835_FSEL_ALT4>;
+			bias-disable;
+		};
+	};
+};
+
+&vec {
+	interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&usb {
+	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&hdmi {
+	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+		     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&uart1 {
+	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&spi1 {
+	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&spi2 {
+	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&sdhci {
+	interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c0 {
+	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c1 {
+	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&i2c2 {
+	interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&mailbox {
+	interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&sdhost {
+	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&uart0 {
+	interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&txp {
+	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+};
diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
index 1104e4c..8dbddff 100644
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@ -53,7 +53,7 @@
 		#address-cells = <1>;
 		#size-cells = <1>;

-		txp@7e004000 {
+		txp: txp@7e004000 {
 			compatible = "brcm,bcm2835-txp";
 			reg = <0x7e004000 0x20>;
 			interrupts = <1 11>;
--
2.7.4


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Re: [PATCH RFC 18/18] ARM: dts: Add minimal Raspberry Pi 4 support

[Florian Fainelli]

On 7/17/2019 2:16 PM, Stefan Wahren wrote:
> This adds minimal support for the new Raspberry Pi 4 without the
> fancy stuff like GENET, PCIe, XHCI, 40 bit DMA and V3D. The RPi 4 is avail=
> able
> in 3 different variants (1, 2 and 4 GB RAM), so leave the memory size to z=
> ero
> and let the bootloader take care of it.
> 
> Other differences to the Raspberry Pi 3:
> - additional GIC 400 Interrupt controller
> - new thermal IP and HWRNG
> - additional MMC interface (emmc2)
> - additional UART, I2C, SPI and PWM interfaces
> 
> Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
> =2D--

[snip]

> +		rng@7e104000 {
> +			interrupts =3D <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
> +
> +			/* RNG is incompatible to brcm,bcm2835-rng */
> +			status =3D "disabled";

It's an iproc-rng200, so you can either re-use the bcm7211-rng
compatible string that was just recently added or you can define a
bcm2838-rng if you prefer.
-- 
Florian

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Re: [PATCH RFC 18/18] ARM: dts: Add minimal Raspberry Pi 4 support

[Stefan Wahren]

Hi Florian,

Am 17.07.19 um 23:22 schrieb Florian Fainelli:
>
> On 7/17/2019 2:16 PM, Stefan Wahren wrote:
>> This adds minimal support for the new Raspberry Pi 4 without the
>> fancy stuff like GENET, PCIe, XHCI, 40 bit DMA and V3D. The RPi 4 is avail=
>> able
>> in 3 different variants (1, 2 and 4 GB RAM), so leave the memory size to z=
>> ero
>> and let the bootloader take care of it.
>>
>> Other differences to the Raspberry Pi 3:
>> - additional GIC 400 Interrupt controller
>> - new thermal IP and HWRNG
>> - additional MMC interface (emmc2)
>> - additional UART, I2C, SPI and PWM interfaces
>>
>> Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
>> =2D--
> [snip]
>
>> +		rng@7e104000 {
>> +			interrupts =3D <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> +			/* RNG is incompatible to brcm,bcm2835-rng */
>> +			status =3D "disabled";
> It's an iproc-rng200, so you can either re-use the bcm7211-rng
> compatible string that was just recently added or you can define a
> bcm2838-rng if you prefer.

i know [1], but this is not essential and the series is long enough.

Thanks
Stefan

[1] -
https://github.com/raspberrypi/linux/commit/5e74aadfd1e0e6c00994521863ba044ce25b40de#diff-472f0181289458c487c07a343f767a81


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Re: [PATCH RFC 15/18] spi: bcm2835: enable shared interrupt support

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 267 bytes --]

On Wed, Jul 17, 2019 at 11:16:01PM +0200, Stefan Wahren wrote:

> +	/* check if we got interrupt enabled */
> +	if (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_INTR))
> +		return IRQ_NONE;
> +

Is that checking if the interrupt is enabled or if it is asserted?

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Re: [PATCH RFC 15/18] spi: bcm2835: enable shared interrupt support

[Stefan Wahren]

Hi Mark,

Am 18.07.19 um 14:42 schrieb Mark Brown:
> On Wed, Jul 17, 2019 at 11:16:01PM +0200, Stefan Wahren wrote:
>
>> +	/* check if we got interrupt enabled */
>> +	if (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_INTR))
>> +		return IRQ_NONE;
>> +
> Is that checking if the interrupt is enabled or if it is asserted?

the BCM2835 doesn't provide a SPI register, which shows that the
interrupt has been asserted.

So i think, Martin tried to adapt the workaround from spi-bcm2835-aux
which has the same problem.

Stefan


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Re: [PATCH RFC 15/18] spi: bcm2835: enable shared interrupt support

[Florian Fainelli]

On 7/18/19 10:53 AM, Stefan Wahren wrote:
> Hi Mark,
> 
> Am 18.07.19 um 14:42 schrieb Mark Brown:
>> On Wed, Jul 17, 2019 at 11:16:01PM +0200, Stefan Wahren wrote:
>>
>>> +	/* check if we got interrupt enabled */
>>> +	if (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_INTR))
>>> +		return IRQ_NONE;
>>> +
>> Is that checking if the interrupt is enabled or if it is asserted?
> 
> the BCM2835 doesn't provide a SPI register, which shows that the
> interrupt has been asserted.
> 
> So i think, Martin tried to adapt the workaround from spi-bcm2835-aux
> which has the same problem.

I was about to submit a change to address that since we also have that
shared interrupt on BCM7211:

https://github.com/ffainelli/linux/commit/15d96d82bd42991dc71369128131312d5338f65c

Martin's patch is more efficient in terms of amount of register
accesses, but I am bit worried (based on the register description) that
the INTR bit is only asserted with the read FIFO crossing a certain
condition and that a TX only transfer may not be captured by that condition.

Maybe we can just check spi_controller::idling to determine if that
specific instance generated an interrupt?
-- 
Florian

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Re: [PATCH RFC 15/18] spi: bcm2835: enable shared interrupt support

[Stefan Wahren]

Hi Florian,

Am 18.07.19 um 20:05 schrieb Florian Fainelli:
> On 7/18/19 10:53 AM, Stefan Wahren wrote:
>> Hi Mark,
>>
> I was about to submit a change to address that since we also have that
> shared interrupt on BCM7211:
>
> https://github.com/ffainelli/linux/commit/15d96d82bd42991dc71369128131312d5338f65c
>
> Martin's patch is more efficient in terms of amount of register
> accesses, but I am bit worried (based on the register description) that
> the INTR bit is only asserted with the read FIFO crossing a certain
> condition and that a TX only transfer may not be captured by that condition.
>
> Maybe we can just check spi_controller::idling to determine if that
> specific instance generated an interrupt?

sorry, i'm not that SPI expert. I suggest to drop this non-essential
patch from the series and discuss this separate.

Stefan


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Re: [PATCH RFC 15/18] spi: bcm2835: enable shared interrupt support

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 976 bytes --]

On Thu, Jul 18, 2019 at 07:53:43PM +0200, Stefan Wahren wrote:
> Am 18.07.19 um 14:42 schrieb Mark Brown:
> > On Wed, Jul 17, 2019 at 11:16:01PM +0200, Stefan Wahren wrote:

> >> +	/* check if we got interrupt enabled */
> >> +	if (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_INTR))
> >> +		return IRQ_NONE;

> > Is that checking if the interrupt is enabled or if it is asserted?

> the BCM2835 doesn't provide a SPI register, which shows that the
> interrupt has been asserted.

> So i think, Martin tried to adapt the workaround from spi-bcm2835-aux
> which has the same problem.

OK, I don't know what that workaround was or exactly what this is
checking but if it's just checking if the interrupt was enabled then
there's going to be cases where this gets called while interrupts are
enabled but due to another device asserting the interrupt.  If the
driver can cope with that and this is just an optimization then fine but
if it's relying on this there's an issue.

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Re: [PATCH RFC 18/18] ARM: dts: Add minimal Raspberry Pi 4 support

[Marc Zyngier]

On Wed, 17 Jul 2019 23:16:04 +0200
Stefan Wahren <wahrenst@gmx.net> wrote:

> This adds minimal support for the new Raspberry Pi 4 without the
> fancy stuff like GENET, PCIe, XHCI, 40 bit DMA and V3D. The RPi 4 is available
> in 3 different variants (1, 2 and 4 GB RAM), so leave the memory size to zero
> and let the bootloader take care of it.
> 
> Other differences to the Raspberry Pi 3:
> - additional GIC 400 Interrupt controller
> - new thermal IP and HWRNG
> - additional MMC interface (emmc2)
> - additional UART, I2C, SPI and PWM interfaces
> 
> Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
> ---
>  arch/arm/boot/dts/Makefile            |   1 +
>  arch/arm/boot/dts/bcm2838-rpi-4-b.dts | 120 +++++++
>  arch/arm/boot/dts/bcm2838.dtsi        | 657 ++++++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/bcm283x.dtsi        |   2 +-
>  4 files changed, 779 insertions(+), 1 deletion(-)
>  create mode 100644 arch/arm/boot/dts/bcm2838-rpi-4-b.dts
>  create mode 100644 arch/arm/boot/dts/bcm2838.dtsi
> 

[...]

> diff --git a/arch/arm/boot/dts/bcm2838.dtsi b/arch/arm/boot/dts/bcm2838.dtsi
> new file mode 100644
> index 0000000..e004d70
> --- /dev/null
> +++ b/arch/arm/boot/dts/bcm2838.dtsi
> @@ -0,0 +1,657 @@
> +// SPDX-License-Identifier: GPL-2.0
> +#include "bcm283x.dtsi"
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/soc/bcm2835-pm.h>
> +
> +/ {
> +	compatible = "brcm,bcm2838";
> +
> +	#address-cells = <2>;
> +	#size-cells = <1>;
> +
> +	interrupt-parent = <&gicv2>;
> +
> +	soc {
> +		ranges = <0x7e000000  0x0 0xfe000000  0x01800000>,
> +			 <0x7c000000  0x0 0xfc000000  0x02000000>,
> +			 <0x40000000  0x0 0xff800000  0x00800000>;
> +		/* Emulate a contiguous 30-bit address range for DMA */
> +		dma-ranges = <0xc0000000  0x0 0x00000000  0x3c000000>;
> +
> +		local_intc: local_intc@40000000 {
> +			compatible = "brcm,bcm2836-l1-intc";
> +			reg = <0x40000000 0x100>;
> +		};
> +
> +		gicv2: gic400@40041000 {
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			compatible = "arm,gic-400";
> +			reg =	<0x40041000 0x1000>,
> +				<0x40042000 0x2000>,
> +				<0x40044000 0x2000>,
> +				<0x40046000 0x2000>;

Missing maintenance interrupt (usually on PPI9).

> +		};

[...]

> +	arm-pmu {
> +		/*
> +		 * N.B. the A72 PMU support only exists in arch/arm64, hence
> +		 * the fallback to the A53 version.
> +		 */
> +		compatible = "arm,cortex-a72-pmu", "arm,cortex-a53-pmu";

You're thus guaranteed to count the wrong events... And you could at
least have "arm,armv8-pmuv3".

> +		interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
> +			<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
> +			<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> +			<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;

You're missing the interrupt-affinity property.

> +	};
> +
> +	timer {
> +		compatible = "arm,armv7-timer";
> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
> +					  IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
> +					  IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
> +					  IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
> +					  IRQ_TYPE_LEVEL_LOW)>;
> +		arm,cpu-registers-not-fw-configured;

Really? :-(

> +		always-on;

I'm pretty sure that's not the case. This indicates that you can power
the CPU off, bring it back on, and yet have your timer alive and
kicking. The only case this actually exists is for VMs. I can see it
being cargo-culted from previous RPi revisions, but that doesn't make
it true.

Thanks,

	M.
-- 
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Re: [PATCH RFC 18/18] ARM: dts: Add minimal Raspberry Pi 4 support

[Vladimir Murzin]

On 7/23/19 7:13 PM, Marc Zyngier wrote:
>> +	arm-pmu {
>> +		/*
>> +		 * N.B. the A72 PMU support only exists in arch/arm64, hence
>> +		 * the fallback to the A53 version.
>> +		 */
>> +		compatible = "arm,cortex-a72-pmu", "arm,cortex-a53-pmu";
> You're thus guaranteed to count the wrong events... And you could at
> least have "arm,armv8-pmuv3".
> 

Isn't "arm,armv8-pmuv3" still "only exists in arch/arm64" (along with "arm,cortex-a53-pmu")?

P.S.
Yes, I remember you posted some related patches in a past yet they never hit mainline :(

Cheers
Vladimir

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Re: [PATCH RFC 18/18] ARM: dts: Add minimal Raspberry Pi 4 support

[Marc Zyngier]

Hi Vladimir,

On 24/07/2019 10:51, Vladimir Murzin wrote:
> On 7/23/19 7:13 PM, Marc Zyngier wrote:
>>> +	arm-pmu {
>>> +		/*
>>> +		 * N.B. the A72 PMU support only exists in arch/arm64, hence
>>> +		 * the fallback to the A53 version.
>>> +		 */
>>> +		compatible = "arm,cortex-a72-pmu", "arm,cortex-a53-pmu";
>> You're thus guaranteed to count the wrong events... And you could at
>> least have "arm,armv8-pmuv3".
>>
> 
> Isn't "arm,armv8-pmuv3" still "only exists in arch/arm64" (along with "arm,cortex-a53-pmu")?

Absolutely. And yet this is describing the HW, not the shortcomings of
the kernel. I want to be able to take the same DT and run it on the
64bit kernel.

> P.S.
> Yes, I remember you posted some related patches in a past yet they never hit mainline :(

Will wanted me to repaint the whole of the 32bit perf code. I may end-up
doing that in the future if I get some idle time (but don't hold your
breath).

	M.
-- 
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Re: [PATCH RFC 18/18] ARM: dts: Add minimal Raspberry Pi 4 support

[Vladimir Murzin]

Hi Marc,

On 7/24/19 11:41 AM, Marc Zyngier wrote:
> Hi Vladimir,
> 
> On 24/07/2019 10:51, Vladimir Murzin wrote:
>> On 7/23/19 7:13 PM, Marc Zyngier wrote:
>>>> +	arm-pmu {
>>>> +		/*
>>>> +		 * N.B. the A72 PMU support only exists in arch/arm64, hence
>>>> +		 * the fallback to the A53 version.
>>>> +		 */
>>>> +		compatible = "arm,cortex-a72-pmu", "arm,cortex-a53-pmu";
>>> You're thus guaranteed to count the wrong events... And you could at
>>> least have "arm,armv8-pmuv3".
>>>
>>
>> Isn't "arm,armv8-pmuv3" still "only exists in arch/arm64" (along with "arm,cortex-a53-pmu")?
> 
> Absolutely. And yet this is describing the HW, not the shortcomings of
> the kernel. I want to be able to take the same DT and run it on the
> 64bit kernel.
> 

Agreed. I was confused by comment block which describes software side of things rather than hardware.

@Stefan, can you, please, update compatible per Marc suggestion, i.e

compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";

and remove that comment block?

>> P.S.
>> Yes, I remember you posted some related patches in a past yet they never hit mainline :(
> 
> Will wanted me to repaint the whole of the 32bit perf code. I may end-up
> doing that in the future if I get some idle time (but don't hold your
> breath).
> 

:)

Thanks
Vladimir

> 	M.
> 


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Re: [PATCH RFC 15/18] spi: bcm2835: enable shared interrupt support

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 1222 bytes --]

On Thu, Jul 18, 2019 at 08:21:36PM +0200, Stefan Wahren wrote:
> Am 18.07.19 um 20:05 schrieb Florian Fainelli:
> > On 7/18/19 10:53 AM, Stefan Wahren wrote:

> > Martin's patch is more efficient in terms of amount of register
> > accesses, but I am bit worried (based on the register description) that
> > the INTR bit is only asserted with the read FIFO crossing a certain
> > condition and that a TX only transfer may not be captured by that condition.

It looks like the driver sets the bit for TX only transfers so that's
probably fine but I might be missing something.

> > Maybe we can just check spi_controller::idling to determine if that
> > specific instance generated an interrupt?

> sorry, i'm not that SPI expert. I suggest to drop this non-essential
> patch from the series and discuss this separate.

I'm not opposed to the patch, I'm just concerned based on the
combination of the description and the code that it might not be doing
what's expected.  If it's mostly just an optimization that provides a
fast path in the case the interrupt is shared rather than a correctness
thing then it's fine.  A comment in the commit message or the code about
this being an optimization would be a good idea though.

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[-- Attachment #2: Type: text/plain, Size: 176 bytes --]

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Re: [PATCH RFC 18/18] ARM: dts: Add minimal Raspberry Pi 4 support

[Stefan Wahren]

Hi Vladimir,

Am 24.07.19 um 14:36 schrieb Vladimir Murzin:
> Hi Marc,
>
> On 7/24/19 11:41 AM, Marc Zyngier wrote:
>> Hi Vladimir,
>>
>> On 24/07/2019 10:51, Vladimir Murzin wrote:
>>> On 7/23/19 7:13 PM, Marc Zyngier wrote:
>>>>> +	arm-pmu {
>>>>> +		/*
>>>>> +		 * N.B. the A72 PMU support only exists in arch/arm64, hence
>>>>> +		 * the fallback to the A53 version.
>>>>> +		 */
>>>>> +		compatible = "arm,cortex-a72-pmu", "arm,cortex-a53-pmu";
>>>> You're thus guaranteed to count the wrong events... And you could at
>>>> least have "arm,armv8-pmuv3".
>>>>
>>> Isn't "arm,armv8-pmuv3" still "only exists in arch/arm64" (along with "arm,cortex-a53-pmu")?
>> Absolutely. And yet this is describing the HW, not the shortcomings of
>> the kernel. I want to be able to take the same DT and run it on the
>> 64bit kernel.
>>
> Agreed. I was confused by comment block which describes software side of things rather than hardware.
>
> @Stefan, can you, please, update compatible per Marc suggestion, i.e
>
> compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
>
> and remove that comment block?

yes, i will do in the next version of the series. I also got some
feedback about the rest of Marc's comments.

Btw you are commenting on a older version of this series, but the
mentioned parts are not affected.

Stefan


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Re: [PATCH RFC 18/18] ARM: dts: Add minimal Raspberry Pi 4 support

[Stefan Wahren]

Hi Marc,

Am 23.07.19 um 20:13 schrieb Marc Zyngier:
> On Wed, 17 Jul 2019 23:16:04 +0200
> Stefan Wahren <wahrenst@gmx.net> wrote:
>
>> This adds minimal support for the new Raspberry Pi 4 without the
>> fancy stuff like GENET, PCIe, XHCI, 40 bit DMA and V3D. The RPi 4 is available
>> in 3 different variants (1, 2 and 4 GB RAM), so leave the memory size to zero
>> and let the bootloader take care of it.
>>
>> Other differences to the Raspberry Pi 3:
>> - additional GIC 400 Interrupt controller
>> - new thermal IP and HWRNG
>> - additional MMC interface (emmc2)
>> - additional UART, I2C, SPI and PWM interfaces
>>
>> Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
>>
>> ...
>> +	};
>> +
>> +	timer {
>> +		compatible = "arm,armv7-timer";
>> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
>> +					  IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
>> +					  IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
>> +					  IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
>> +					  IRQ_TYPE_LEVEL_LOW)>;
>> +		arm,cpu-registers-not-fw-configured;
> Really? :-(
i asked about that [1] and they said that the arm stubs [2] only set the
timer frequency and zeroing CNTVOFF_EL2.
>
>> +		always-on;
> I'm pretty sure that's not the case. This indicates that you can power
> the CPU off, bring it back on, and yet have your timer alive and
> kicking. The only case this actually exists is for VMs. I can see it
> being cargo-culted from previous RPi revisions, but that doesn't make
> it true.

They said that they used this to suppress high interrupt load for the
timers.

Stefan

[1] - https://github.com/raspberrypi/linux/issues/3101
[2] - https://github.com/raspberrypi/tools/blob/master/armstubs/armstub8.S

>
> Thanks,
>
> 	M.


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Re: [PATCH RFC 18/18] ARM: dts: Add minimal Raspberry Pi 4 support

[Marc Zyngier]

Hi Stephan,

On Sun, 28 Jul 2019 11:58:58 +0100,
Stefan Wahren <stefan.wahren@i2se.com> wrote:
> 
> Hi Marc,
> 
> Am 23.07.19 um 20:13 schrieb Marc Zyngier:
> > On Wed, 17 Jul 2019 23:16:04 +0200
> > Stefan Wahren <wahrenst@gmx.net> wrote:
> >
> >> This adds minimal support for the new Raspberry Pi 4 without the
> >> fancy stuff like GENET, PCIe, XHCI, 40 bit DMA and V3D. The RPi 4 is available
> >> in 3 different variants (1, 2 and 4 GB RAM), so leave the memory size to zero
> >> and let the bootloader take care of it.
> >>
> >> Other differences to the Raspberry Pi 3:
> >> - additional GIC 400 Interrupt controller
> >> - new thermal IP and HWRNG
> >> - additional MMC interface (emmc2)
> >> - additional UART, I2C, SPI and PWM interfaces
> >>
> >> Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
> >>
> >> ...
> >> +	};
> >> +
> >> +	timer {
> >> +		compatible = "arm,armv7-timer";

BTW, this should be "arm,armv8-timer".

> >> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
> >> +					  IRQ_TYPE_LEVEL_LOW)>,
> >> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
> >> +					  IRQ_TYPE_LEVEL_LOW)>,
> >> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
> >> +					  IRQ_TYPE_LEVEL_LOW)>,
> >> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
> >> +					  IRQ_TYPE_LEVEL_LOW)>;
> >> +		arm,cpu-registers-not-fw-configured;
> > Really? :-(
> i asked about that [1] and they said that the arm stubs [2] only set the
> timer frequency and zeroing CNTVOFF_EL2.

Who is "they"? As long as it is done on all CPUs, that's the right
thing to do, and this property is pretty useless in that case.

> >
> >> +		always-on;
> > I'm pretty sure that's not the case. This indicates that you can power
> > the CPU off, bring it back on, and yet have your timer alive and
> > kicking. The only case this actually exists is for VMs. I can see it
> > being cargo-culted from previous RPi revisions, but that doesn't make
> > it true.
> 
> They said that they used this to suppress high interrupt load for the
> timers.

Indeed, and that's the only thing the kernel can do if it isn't
provided with a global timer that can be used as a backup then the
CPUs transition to a deep idle state where the timers are not actually
running.

If you have such a global timer, enable it and you'll see the
interrupt rate dropping like a rock. Don't you have a
brcm,bcm2835-system-timer stashed somewhere?

If you don't have such a timer, then the question is whether the CPUs
can go into a deep enough sleep state where the timer comparator is
disabled, leading to missed events. If this system can only reach very
shallow sleep states, then always-on is OK. Otherwise, this is a total
lie and you're likely to miss timer events.

Thanks,

	M.

-- 
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Re: [PATCH RFC 18/18] ARM: dts: Add minimal Raspberry Pi 4 support

[Stefan Wahren]

Hi Marc,
>> Hi Marc,
>>
>> Am 23.07.19 um 20:13 schrieb Marc Zyngier:
>>> On Wed, 17 Jul 2019 23:16:04 +0200
>>> Stefan Wahren <wahrenst@gmx.net> wrote:
>>>
>>>> This adds minimal support for the new Raspberry Pi 4 without the
>>>> fancy stuff like GENET, PCIe, XHCI, 40 bit DMA and V3D. The RPi 4 is available
>>>> in 3 different variants (1, 2 and 4 GB RAM), so leave the memory size to zero
>>>> and let the bootloader take care of it.
>>>>
>>>> Other differences to the Raspberry Pi 3:
>>>> - additional GIC 400 Interrupt controller
>>>> - new thermal IP and HWRNG
>>>> - additional MMC interface (emmc2)
>>>> - additional UART, I2C, SPI and PWM interfaces
>>>>
>>>> Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
>>>>
>>>> ...
>>>> +	};
>>>> +
>>>> +	timer {
>>>> +		compatible = "arm,armv7-timer";
> BTW, this should be "arm,armv8-timer".
>
>>>> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
>>>> +					  IRQ_TYPE_LEVEL_LOW)>,
>>>> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
>>>> +					  IRQ_TYPE_LEVEL_LOW)>,
>>>> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
>>>> +					  IRQ_TYPE_LEVEL_LOW)>,
>>>> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
>>>> +					  IRQ_TYPE_LEVEL_LOW)>;
>>>> +		arm,cpu-registers-not-fw-configured;
>>> Really? :-(
>> i asked about that [1] and they said that the arm stubs [2] only set the
>> timer frequency and zeroing CNTVOFF_EL2.
> Who is "they"? As long as it is done on all CPUs, that's the right
> thing to do, and this property is pretty useless in that case.

"They" are the developer at Raspberry Pi Trading. I forwarded some
questions regarding this topic to them, but didn't get a reply yet. My
current understanding is that the armv8 stubs do setup the timer, but
the armv7 stubs do not. So we probably need to keep it.

>
>>>> +		always-on;
>>> I'm pretty sure that's not the case. This indicates that you can power
>>> the CPU off, bring it back on, and yet have your timer alive and
>>> kicking. The only case this actually exists is for VMs. I can see it
>>> being cargo-culted from previous RPi revisions, but that doesn't make
>>> it true.
>> They said that they used this to suppress high interrupt load for the
>> timers.
> Indeed, and that's the only thing the kernel can do if it isn't
> provided with a global timer that can be used as a backup then the
> CPUs transition to a deep idle state where the timers are not actually
> running.
>
> If you have such a global timer, enable it and you'll see the
> interrupt rate dropping like a rock. Don't you have a
> brcm,bcm2835-system-timer stashed somewhere?

I've got the feedback that the system timer still exists. Unfortunately
i don't have the new interrupt definition yet. So i need to wait for
this before sending a new version of this series.

Best regards
Stefan Wahren

>
> If you don't have such a timer, then the question is whether the CPUs
> can go into a deep enough sleep state where the timer comparator is
> disabled, leading to missed events. If this system can only reach very
> shallow sleep states, then always-on is OK. Otherwise, this is a total
> lie and you're likely to miss timer events.
>
> Thanks,
>
> 	M.
>

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Re: [PATCH RFC 18/18] ARM: dts: Add minimal Raspberry Pi 4 support

[Marc Zyngier]

On 30/07/2019 19:33, Stefan Wahren wrote:
> Hi Marc,
>>> Hi Marc,
>>>
>>> Am 23.07.19 um 20:13 schrieb Marc Zyngier:
>>>> On Wed, 17 Jul 2019 23:16:04 +0200
>>>> Stefan Wahren <wahrenst@gmx.net> wrote:
>>>>
>>>>> This adds minimal support for the new Raspberry Pi 4 without the
>>>>> fancy stuff like GENET, PCIe, XHCI, 40 bit DMA and V3D. The RPi 4 is available
>>>>> in 3 different variants (1, 2 and 4 GB RAM), so leave the memory size to zero
>>>>> and let the bootloader take care of it.
>>>>>
>>>>> Other differences to the Raspberry Pi 3:
>>>>> - additional GIC 400 Interrupt controller
>>>>> - new thermal IP and HWRNG
>>>>> - additional MMC interface (emmc2)
>>>>> - additional UART, I2C, SPI and PWM interfaces
>>>>>
>>>>> Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
>>>>>
>>>>> ...
>>>>> +	};
>>>>> +
>>>>> +	timer {
>>>>> +		compatible = "arm,armv7-timer";
>> BTW, this should be "arm,armv8-timer".
>>
>>>>> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
>>>>> +					  IRQ_TYPE_LEVEL_LOW)>,
>>>>> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
>>>>> +					  IRQ_TYPE_LEVEL_LOW)>,
>>>>> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
>>>>> +					  IRQ_TYPE_LEVEL_LOW)>,
>>>>> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
>>>>> +					  IRQ_TYPE_LEVEL_LOW)>;
>>>>> +		arm,cpu-registers-not-fw-configured;
>>>> Really? :-(
>>> i asked about that [1] and they said that the arm stubs [2] only set the
>>> timer frequency and zeroing CNTVOFF_EL2.
>> Who is "they"? As long as it is done on all CPUs, that's the right
>> thing to do, and this property is pretty useless in that case.
> 
> "They" are the developer at Raspberry Pi Trading. I forwarded some
> questions regarding this topic to them, but didn't get a reply yet. My
> current understanding is that the armv8 stubs do setup the timer, but
> the armv7 stubs do not. So we probably need to keep it.

From what I gather, these stubs can be updated (and apparently are
updated regularly). So why not fix them once and for all?

> 
>>
>>>>> +		always-on;
>>>> I'm pretty sure that's not the case. This indicates that you can power
>>>> the CPU off, bring it back on, and yet have your timer alive and
>>>> kicking. The only case this actually exists is for VMs. I can see it
>>>> being cargo-culted from previous RPi revisions, but that doesn't make
>>>> it true.
>>> They said that they used this to suppress high interrupt load for the
>>> timers.
>> Indeed, and that's the only thing the kernel can do if it isn't
>> provided with a global timer that can be used as a backup then the
>> CPUs transition to a deep idle state where the timers are not actually
>> running.
>>
>> If you have such a global timer, enable it and you'll see the
>> interrupt rate dropping like a rock. Don't you have a
>> brcm,bcm2835-system-timer stashed somewhere?
> 
> I've got the feedback that the system timer still exists. Unfortunately
> i don't have the new interrupt definition yet. So i need to wait for
> this before sending a new version of this series.

Sure, no problem. I also wonder whether the SoC has the memory-mapped
generic timer, which would make a lot of sense...

Thanks,

	M.
-- 
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Re: [PATCH RFC 14/18] HACK: pinctrl: bcm2835: Implement legacy pull for BCM7211

[Linus Walleij]

On Wed, Jul 17, 2019 at 11:16 PM Stefan Wahren <wahrenst@gmx.net> wrote:

> This temporay hack is necessary to make the BCM2838/7211 work with the legacy
> pull configuration. The better approach is to convert all affected DTS files
> to the generic bias control.
>
> Signed-off-by: Stefan Wahren <wahrenst@gmx.net>

I don't understand this: why do you even need to make a *new* SoC work
with *legacy* bias control? Just use the generic pin configs and be happy.

Or did someone produce a lot of DTS file using the "hack" seen in earlier
patches that you would now have to fix? (Sigh.) That is why they should
discuss with community first I guess.

Yours,
Linus Walleij

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