From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 17923C2D0A3 for ; Wed, 4 Nov 2020 18:03:29 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8B2FA206F4 for ; Wed, 4 Nov 2020 18:03:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="HngloI7V" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8B2FA206F4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ap4fLwd6Xj8lsdudNK8EUbMVnopzC2Zm7QSbYJe+7kE=; b=HngloI7V0N06Nqk+t7cq3bHn4 VR8xvX+rb4vg/BhFcOZmFJnPW1o6WZzORJaqeTpjmCUjGzMxrudpOpTIFtFMYvjlmri4EbcwPDtyY 51rZeSGgZ9if9bzfh8ku9Q/gGVlSebqD2C20zXr8ZwWk0j9jounUoLDpnubdVj7H9MZ6brINhURm5 nlVp309rNJobzj1wTT08O9MqAL9Vgg/hfv4lcIO77JbrNcuQ4FJLK63u/f5nnLesC0eRKMGY1r1DL 15Xp7DPZQUzCo0fcZuFqidESJT76mBQPw/G+zI3Jsc/uZHWKa8NRRKsbMqwu8XxYj/xVmukpzrj1y r5F+qZJQg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kaN7b-0005r8-S8; Wed, 04 Nov 2020 18:02:59 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kaN7X-0005pR-W6 for linux-arm-kernel@lists.infradead.org; Wed, 04 Nov 2020 18:02:57 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3AD34106F; Wed, 4 Nov 2020 10:02:54 -0800 (PST) Received: from [10.57.56.213] (unknown [10.57.56.213]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C01E03F718; Wed, 4 Nov 2020 10:02:51 -0800 (PST) Subject: Re: [PATCH v3 0/3] CPUFreq: Add support for cpu performance dependencies To: Viresh Kumar , vincent.guittot@linaro.org References: <20201102120115.29993-1-nicola.mazzucato@arm.com> <20201103101840.yrgwmcjrnjn7n5q6@vireshk-i7> From: Nicola Mazzucato Message-ID: <87558fa9-a4c6-38c9-bcc5-f736c0229f56@arm.com> Date: Wed, 4 Nov 2020 18:04:30 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: <20201103101840.yrgwmcjrnjn7n5q6@vireshk-i7> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201104_130256_217886_4B4DBFB2 X-CRM114-Status: GOOD ( 27.58 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: nm@ti.com, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, sboyd@kernel.org, vireshk@kernel.org, daniel.lezcano@linaro.org, rjw@rjwysocki.net, linux-kernel@vger.kernel.org, robh+dt@kernel.org, sudeep.holla@arm.com, chris.redpath@arm.com, Ionela Voinescu , morten.rasmussen@arm.com, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Viresh, thanks for looking into this. On 11/3/20 10:18 AM, Viresh Kumar wrote: > On 02-11-20, 12:01, Nicola Mazzucato wrote: >> Hi All, >> >> In this V3 posting I have replaced the new dt-binding with minor changes/ >> improvements for opp (since we are now using opp tables instead). >> The RFC still stands on how to make this info available to sw consumers. >> >> In the RFC, I am proposing a simple addition of a performance dependencies >> cpumask in CPUFreq core and an example of how drivers and consumers would >> make use of it. >> I also propose an alternative approach, which does not require changes in >> CPUFreq core, but - possibly - in all the consumers. >> >> This is to support systems where exposed cpu performance controls are more >> fine-grained that the platform's ability to scale cpus independently. > > I was talking to Vincent about what you are doing here and we got a > bit confused and so here are few questions that we had: > > - Based on my previous understanding, you don't want software > coordination of frequencies (which is done by cpufreq today), but > want the hardware to do that and so you want per-cpu cpufreq > policies. Correct. And this has been done for quite some time in some platforms. > > - What's the real benefit of hardware coordination ? Want to make sure > I fully understand that. The hardware coordination that is coming out by having per-cpu cpufreq policies is not new, and works just fine in most of the systems. The benefit of having per-cpu controls is that the firmware will take care of the performance of the entire system. It is purely a delegation to firmware for the performance optimizations. > > - Because of hardware co-ordination of otherwise co-ordinated CPUs, > few things break. Thermal and EAS are some of the examples and so > you are trying to fix them here by proving them the missing > information again. Correct. And for this I have proposed two ways. > > - One other thing that breaks with this is freq-invariance in the > scheduler, as the scheduler won't see the real frequencies the > various CPUs are running at. Most of the hardware we have today > doesn't have counters, like AMUs, not sure if all future ones based > on SCMI will have that too, so how are they gong to be fixed ? > Correct. freq-invariance without counters is trying to do its best based on the information it has available. It definitely relies on the knowledge of the v/f domains to work at its best so I think in the case of per-cpu it will follow the same approach as others being affected (EAS, thermal). > And if we even have to fix this (freq invariance), what's hardware > coordination giving us that makes all this worth it ? I suppose this is more a generic question for all the platforms running with h/w coordination, but for our case is that the f/w will take care of the performance optimizations for us :) > > Sorry about the long list :) No problem at all. Thank you for your time on this and I hope I have made bits clearer. Nicola > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel