From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CF9CC432BE for ; Thu, 26 Aug 2021 08:53:00 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0101B6108F for ; Thu, 26 Aug 2021 08:52:59 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 0101B6108F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=PVZgtYnsYv+Pq8mRaHPf8elQeNfuPIsgPHWywFOIjqg=; b=Ynoivyz7WXSu+b cVrL4JIWyk05PF172OCdY/145kXiIidkMizO9YEpJA1Id2ru/lKNVsZv8J0tvNmpqk765XC21N0TE uk7hXBYliB8dVjzWOp7w7aivvRnryZ9VXou5mkIkoz3TjchRuOWNfNkbOKacD40PLXZADGGeq+edd mmlH1W+c0Ycwqxi3fy1wptVdv7IZjbRg3FlD3FEUX1tyfNBfDJa+ZacuV80JLwCIAg29QQMe9LimQ voWAddybKSWUgulbjm9z+Xj7Ytmbsk1HKiundg04FMnQNg5G/0MNMz3PWES5q3HI+ZkyMvEFs/q38 sGIpXTCWNXP5VgLJPKRg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mJB6Q-009aOh-W8; Thu, 26 Aug 2021 08:51:15 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mJB6K-009aO0-IC for linux-arm-kernel@lists.infradead.org; Thu, 26 Aug 2021 08:51:12 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 282DD61076; Thu, 26 Aug 2021 08:51:08 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mJB6I-007JEw-1K; Thu, 26 Aug 2021 09:51:06 +0100 Date: Thu, 26 Aug 2021 09:51:05 +0100 Message-ID: <875yvspp1i.wl-maz@kernel.org> From: Marc Zyngier To: Alexandru Elisei Cc: catalin.marinas@arm.com, will@kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, broonie@kernel.org Subject: Re: [PATCH v2] arm64: Do not trap PMSNEVFR_EL1 In-Reply-To: <20210824154523.906270-1-alexandru.elisei@arm.com> References: <20210824154523.906270-1-alexandru.elisei@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: alexandru.elisei@arm.com, catalin.marinas@arm.com, will@kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, broonie@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210826_015108_662904_C85B419C X-CRM114-Status: GOOD ( 24.70 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 24 Aug 2021 16:45:23 +0100, Alexandru Elisei wrote: > > Commit 31c00d2aeaa2 ("arm64: Disable fine grained traps on boot") zeroed > the fine grained trap registers to prevent unwanted register traps from > occuring. However, for the PMSNEVFR_EL1 register, the corresponding > HDFG{R,W}TR_EL2.nPMSNEVFR_EL1 fields must be 1 to disable trapping. Set > both fields to 1 if FEAT_SPEv1p2 is detected to disable read and write > traps. > > Fixes: 31c00d2aeaa2 ("arm64: Disable fine grained traps on boot") > Signed-off-by: Alexandru Elisei > --- > Based on v5.14-rc7. Tested on the model, using boot-wrapper built from > commit 5cd6238ec4ef ("aarch32: fix .globl replacement"). Without this > patch, in NVHE mode, the model freezes when I try to access PMSNEVFR_EL1. > With this patch, the model doesn't hang anymore. > > Changes since v1: > > * Set the corresponding bit in HDFGWRTR_EL2 to also disable write traps. My > thanks to Mark for pointing it out. > > arch/arm64/include/asm/el2_setup.h | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h > index b83fb24954b7..3198acb2aad8 100644 > --- a/arch/arm64/include/asm/el2_setup.h > +++ b/arch/arm64/include/asm/el2_setup.h > @@ -149,8 +149,17 @@ > ubfx x1, x1, #ID_AA64MMFR0_FGT_SHIFT, #4 > cbz x1, .Lskip_fgt_\@ > > - msr_s SYS_HDFGRTR_EL2, xzr > - msr_s SYS_HDFGWTR_EL2, xzr > + mov x0, xzr > + mrs x1, id_aa64dfr0_el1 > + ubfx x1, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4 > + cmp x1, #3 > + b.lt .Lset_fgt_\@ > + /* Disable PMSNEVFR_EL1 read and write traps */ > + orr x0, x0, #(1 << 62) > + > +.Lset_fgt_\@: > + msr_s SYS_HDFGRTR_EL2, x0 > + msr_s SYS_HDFGWTR_EL2, x0 > msr_s SYS_HFGRTR_EL2, xzr > msr_s SYS_HFGWTR_EL2, xzr > msr_s SYS_HFGITR_EL2, xzr The beauty of negative trap bits... Thankfully this seems to be the only one. Acked-by: Marc Zyngier M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel