From: Marc Zyngier <maz@kernel.org>
To: Shanker R Donthineni <sdonthineni@nvidia.com>
Cc: Alex Williamson <alex.williamson@redhat.com>,
Will Deacon <will@kernel.org>,
"Catalin\ Marinas" <catalin.marinas@arm.com>,
Christoffer Dall <christoffer.dall@arm.com>,
<linux-arm-kernel@lists.infradead.org>,
<kvmarm@lists.cs.columbia.edu>, <linux-kernel@vger.kernel.org>,
<kvm@vger.kernel.org>, Vikram Sethi <vsethi@nvidia.com>,
Jason Sequeira <jsequeira@nvidia.com>
Subject: Re: [RFC 1/2] vfio/pci: keep the prefetchable attribute of a BAR region in VMA
Date: Fri, 30 Apr 2021 12:47:43 +0100 [thread overview]
Message-ID: <87czucngdc.wl-maz@kernel.org> (raw)
In-Reply-To: <e3d7fda8-5263-211c-3686-f699765ab715@nvidia.com>
Hi Shanker,
On Fri, 30 Apr 2021 12:25:08 +0100,
Shanker R Donthineni <sdonthineni@nvidia.com> wrote:
>
> Hi Alex
>
> On 4/29/21 2:46 PM, Alex Williamson wrote:
> > If an alignment fault is fixed by configuring a WC mapping, doesn't
> > that suggest that the driver performed an unaligned access itself and
> > is relying on write combining by the processor to correct that error?
> > That's wrong. Fix the driver or please offer another explanation of
> > how the WC mapping resolves this. I suspect you could enable tracing
> > in QEMU, disable MMIO mmaps on the vfio-pci device and find the invalid
> > access.
> >
> >> We've two concerns here:
> >> - Performance impacts for pass-through devices.
> >> - The definition of ioremap_wc() function doesn't match the host
> >> kernel on ARM64
> > Performance I can understand, but I think you're also using it to mask
> > a driver bug which should be resolved first. Thank
>
> We’ve already instrumented the driver code and found the code path
> for the unaligned accesses. We’ll fix this issue if it’s not
> following WC semantics.
>
> Fixing the performance concern will be under KVM stage-2 page-table
> control. We're looking for a guidance/solution for updating stage-2
> PTE based on PCI-BAR attribute.
Before we start discussing the *how*, I'd like to clearly understand
what *arm64* memory attributes you are relying on. We already have
established that the unaligned access was a bug, which was the biggest
argument in favour of NORMAL_NC. What are the other requirements?
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
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next prev parent reply other threads:[~2021-04-30 11:49 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-29 16:29 [RFC 0/2] [RFC] Honor PCI prefetchable attributes for a virtual machine on ARM64 Shanker Donthineni
2021-04-29 16:29 ` [RFC 1/2] vfio/pci: keep the prefetchable attribute of a BAR region in VMA Shanker Donthineni
2021-04-29 18:28 ` Alex Williamson
2021-04-29 19:14 ` Shanker R Donthineni
2021-04-29 19:46 ` Alex Williamson
2021-04-29 22:08 ` Vikram Sethi
2021-04-30 11:25 ` Shanker R Donthineni
2021-04-30 11:47 ` Marc Zyngier [this message]
2021-04-30 13:07 ` Shanker R Donthineni
2021-04-30 15:07 ` Marc Zyngier
2021-04-30 14:58 ` Shanker R Donthineni
2021-04-30 15:31 ` Marc Zyngier
2021-04-30 16:57 ` Vikram Sethi
2021-05-01 9:30 ` Marc Zyngier
2021-05-01 11:36 ` Shanker R Donthineni
2021-05-03 9:50 ` Marc Zyngier
2021-05-03 12:08 ` Shanker R Donthineni
2021-05-02 17:56 ` Vikram Sethi
2021-05-03 10:17 ` Marc Zyngier
2021-05-03 13:35 ` Mark Kettenis
2021-05-03 13:59 ` Vikram Sethi
2021-05-03 14:44 ` Alex Williamson
2021-05-03 22:03 ` Vikram Sethi
2021-05-04 8:30 ` Will Deacon
2021-05-05 18:02 ` Catalin Marinas
2021-05-06 7:22 ` Christoph Hellwig
2021-05-08 16:33 ` Shanker R Donthineni
2021-06-02 9:37 ` Marc Zyngier
2021-05-04 18:03 ` Alex Williamson
2021-06-02 9:11 ` Marc Zyngier
2021-04-30 9:54 ` Lorenzo Pieralisi
2021-04-30 12:38 ` Jason Gunthorpe
2021-04-29 16:29 ` [RFC 2/2] KVM: arm64: Add write-combine support for stage-2 entries Shanker Donthineni
2021-05-03 7:01 ` [RFC 0/2] [RFC] Honor PCI prefetchable attributes for a virtual machine on ARM64 Christoph Hellwig
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