From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB580C433E0 for ; Sat, 6 Feb 2021 14:00:04 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 780F664EAD for ; Sat, 6 Feb 2021 14:00:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 780F664EAD Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To:Subject:To:From: Message-ID:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=a3M6otyXuljuW0LvEcr64hntzNPWuPgcMpWa9iYN8tg=; b=D7Md9FMoyNvk7EkyQBq9S8mnR BoEe7F65LNt9dLeWKhCX7LvzC1zhmVkLzNqmibv1mQa//hwgzkRjCDZXfKSfwxd/COolgLROCil5N /pXzc4Z/CE+lCMDvBiOIhSHaCbEJmkam+mAvrPCz5L5di6+nMZzxdyTkTj+jlQ2HZTwW+HgitBu97 mJ9Qz25BJaineC0Eu6X9WT/ZCSpkfvV8Ye+Lv8TGHf2KmPnjsTwYqbX6sYUXc7OSoRcT4L/qKFcpF CEPXZGuXsi3/PYfp+Co/o6aLfrXeYUUs7RLqkTuqVsF98KGQf7If4lkdSRF2dRRtuq8aQdVUwoDsi 73h/bcYuQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l8O6q-0005B2-7U; Sat, 06 Feb 2021 13:58:48 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l8O6n-0005AF-Ua for linux-arm-kernel@lists.infradead.org; Sat, 06 Feb 2021 13:58:46 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 12F8864EBC; Sat, 6 Feb 2021 13:58:45 +0000 (UTC) Received: from 78.163-31-62.static.virginmediabusiness.co.uk ([62.31.163.78] helo=wait-a-minute.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94) (envelope-from ) id 1l8O6k-00CUk7-U6; Sat, 06 Feb 2021 13:58:43 +0000 Date: Sat, 06 Feb 2021 13:58:42 +0000 Message-ID: <87im75l2lp.wl-maz@kernel.org> From: Marc Zyngier To: Hector Martin Subject: Re: [PATCH 08/18] arm64: cpufeature: Add a feature for FIQ support In-Reply-To: <20210204203951.52105-9-marcan@marcan.st> References: <20210204203951.52105-1-marcan@marcan.st> <20210204203951.52105-9-marcan@marcan.st> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 62.31.163.78 X-SA-Exim-Rcpt-To: marcan@marcan.st, soc@kernel.org, linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, arnd@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, olof@lixom.net X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210206_085846_134935_F9FD7DF5 X-CRM114-Status: GOOD ( 34.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , List-Id: Cc: Arnd Bergmann , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, soc@kernel.org, robh+dt@kernel.org, Olof Johansson , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Hector, On Thu, 04 Feb 2021 20:39:41 +0000, Hector Martin wrote: > > Apple ARM SoCs (A11 and newer) have some interrupt sources hard-wired to > the FIQ line. Introduce a cpufeature that can be used to enable FIQ > unmasking and handling via alternatives. > > This is currently enabled for all Apple CPUs. If/when support is > implemented for older (pre-A11) iPhone/iPad SoCs which do not need FIQs, > or if newer SoCs are released without the FIQ requirement, we can > revisit the condition. > > Signed-off-by: Hector Martin > --- > arch/arm64/Kconfig | 10 +++++++++ > arch/arm64/include/asm/cpucaps.h | 3 ++- > arch/arm64/include/asm/cpufeature.h | 6 ++++++ > arch/arm64/include/asm/cputype.h | 1 + > arch/arm64/kernel/cpufeature.c | 32 +++++++++++++++++++++++++++++ > 5 files changed, 51 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index f39568b28ec1..11cfdc07404f 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -1756,6 +1756,16 @@ config ARM64_DEBUG_PRIORITY_MASKING > If unsure, say N > endif > > +config ARM64_FIQ_SUPPORT > + bool "Support for FIQ interrupts" > + help > + Adds support for handling FIQ interrupts as normal IRQs. > + This is required on Apple platforms where some IRQ sources are > + hardwired to the FIQ interrupt line. > + > + FIQs are only enabled at runtime on platforms that require them > + via the CPU feature framework. > + This definitely should be selected by CONFIG_ARCH_APPLE. Otherwise, you can easily end-up with a non-working system. > config RELOCATABLE > bool "Build a relocatable kernel image" if EXPERT > select ARCH_HAS_RELR > diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h > index b77d997b173b..c36d926ad801 100644 > --- a/arch/arm64/include/asm/cpucaps.h > +++ b/arch/arm64/include/asm/cpucaps.h > @@ -66,7 +66,8 @@ > #define ARM64_WORKAROUND_1508412 58 > #define ARM64_HAS_LDAPR 59 > #define ARM64_KVM_PROTECTED_MODE 60 > +#define ARM64_NEEDS_FIQ 61 > > -#define ARM64_NCAPS 61 > +#define ARM64_NCAPS 62 > > #endif /* __ASM_CPUCAPS_H */ > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h > index 9a555809b89c..3a00cfb347c9 100644 > --- a/arch/arm64/include/asm/cpufeature.h > +++ b/arch/arm64/include/asm/cpufeature.h > @@ -716,6 +716,12 @@ static __always_inline bool system_uses_irq_prio_masking(void) > cpus_have_const_cap(ARM64_HAS_IRQ_PRIO_MASKING); > } > > +static __always_inline bool system_uses_fiqs(void) nit: fiq, not fiqs. > +{ > + return IS_ENABLED(CONFIG_ARM64_FIQ_SUPPORT) && > + cpus_have_const_cap(ARM64_NEEDS_FIQ); > +} > + > static inline bool system_supports_mte(void) > { > return IS_ENABLED(CONFIG_ARM64_MTE) && > diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h > index ef5b040dee44..2084a0340d16 100644 > --- a/arch/arm64/include/asm/cputype.h > +++ b/arch/arm64/include/asm/cputype.h > @@ -59,6 +59,7 @@ > #define ARM_CPU_IMP_NVIDIA 0x4E > #define ARM_CPU_IMP_FUJITSU 0x46 > #define ARM_CPU_IMP_HISI 0x48 > +#define ARM_CPU_IMP_APPLE 0x61 > > #define ARM_CPU_PART_AEM_V8 0xD0F > #define ARM_CPU_PART_FOUNDATION 0xD00 > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index e99eddec0a46..0863cf7cf807 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -1237,6 +1237,29 @@ static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, > return ctr & BIT(CTR_IDC_SHIFT); > } > > +static void cpu_sync_irq_to_fiq(struct arm64_cpu_capabilities const *cap) > +{ > + u64 daif = read_sysreg(daif); > + > + /* > + * By this point in the boot process IRQs are likely masked and FIOs > + * aren't, so we need to sync things to avoid spurious early FIQs. > + */ > + > + if (daif & PSR_I_BIT) > + daif |= PSR_F_BIT; > + else > + daif &= ~PSR_F_BIT; > + > + write_sysreg(daif, daif); Could this happen too late? If, as explained above, we can get a FIQ until we mask it here, what prevents something (a timer?) from kicking and creating havoc just before the sync? If the answer is "nothing", then it probably means that the default behaviour should be to treat PSTATE.I and PSTATE.F as containing the same value at all times, and not just as an afterthought when we detect that we're on a CPU type or another. This could expand into enabling Group-0 interrupts with GICv3 on systems that have a single security state (such as virtual machines), though I don't really see a good use case for it. > +} > + > +static bool needs_fiq(const struct arm64_cpu_capabilities *entry, int __unused) > +{ > + /* All supported Apple cores need this */ > + return read_cpuid_implementor() == ARM_CPU_IMP_APPLE; > +} > + > static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) > { > /* > @@ -2154,6 +2177,15 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .matches = has_cpuid_feature, > .min_field_value = 1, > }, > +#ifdef CONFIG_ARM64_FIQ_SUPPORT > + { > + .desc = "FIQs", > + .capability = ARM64_NEEDS_FIQ, > + .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, > + .matches = needs_fiq, > + .cpu_enable = cpu_sync_irq_to_fiq, > + }, > +#endif > {}, > }; Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel