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Wed, 07 Sep 2022 13:14:55 +0100 Date: Wed, 07 Sep 2022 13:14:54 +0100 Message-ID: <87k06fv0sh.wl-maz@kernel.org> From: Marc Zyngier To: Robin Murphy Cc: Jason Gunthorpe , Nipun Gupta , robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, gregkh@linuxfoundation.org, rafael@kernel.org, eric.auger@redhat.com, alex.williamson@redhat.com, cohuck@redhat.com, puneet.gupta@amd.com, song.bao.hua@hisilicon.com, mchehab+huawei@kernel.org, f.fainelli@gmail.com, jeffrey.l.hugo@gmail.com, saravanak@google.com, Michael.Srba@seznam.cz, mani@kernel.org, yishaih@nvidia.com, will@kernel.org, joro@8bytes.org, masahiroy@kernel.org, ndesaulniers@google.com, linux-arm-kernel@lists.infradead.org, linux-kbuild@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, okaya@kernel.org, harpreet.anand@amd.com, nikhil.agarwal@amd.com, michal.simek@amd.com, aleksandar.radovanovic@amd.com, git@amd.com Subject: Re: [RFC PATCH v3 4/7] bus/cdx: add cdx-MSI domain with gic-its domain as parent In-Reply-To: <4ca6383e-bd21-59bf-cc4e-cf3313164957@arm.com> References: <20220803122655.100254-1-nipun.gupta@amd.com> <20220906134801.4079497-1-nipun.gupta@amd.com> <20220906134801.4079497-5-nipun.gupta@amd.com> <87leqvv3g7.wl-maz@kernel.org> <4ca6383e-bd21-59bf-cc4e-cf3313164957@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: robin.murphy@arm.com, jgg@nvidia.com, nipun.gupta@amd.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, gregkh@linuxfoundation.org, rafael@kernel.org, eric.auger@redhat.com, alex.williamson@redhat.com, cohuck@redhat.com, puneet.gupta@amd.com, song.bao.hua@hisilicon.com, mchehab+huawei@kernel.org, f.fainelli@gmail.com, jeffrey.l.hugo@gmail.com, saravanak@google.com, Michael.Srba@seznam.cz, mani@kernel.org, yishaih@nvidia.com, will@kernel.org, joro@8bytes.org, masahiroy@kernel.org, ndesaulniers@google.com, linux-arm-kernel@lists.infradead.org, linux-kbuild@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, okaya@kernel.org, harpreet.anand@amd.com, nikhil.agarwal@amd.com, michal.simek@amd.com, aleksandar.radovanovic@amd.com, git@amd.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220907_051458_528049_963BEC6E X-CRM114-Status: GOOD ( 35.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, 07 Sep 2022 12:33:12 +0100, Robin Murphy wrote: > > On 2022-09-07 12:17, Marc Zyngier wrote: > > On Tue, 06 Sep 2022 18:19:06 +0100, > > Jason Gunthorpe wrote: > >> > >> On Tue, Sep 06, 2022 at 07:17:58PM +0530, Nipun Gupta wrote: > >> > >>> +static void cdx_msi_write_msg(struct irq_data *irq_data, > >>> + struct msi_msg *msg) > >>> +{ > >>> + /* > >>> + * Do nothing as CDX devices have these pre-populated > >>> + * in the hardware itself. > >>> + */ > >>> +} > >> > >> Huh? > >> > >> There is no way it can be pre-populated, the addr/data pair, > >> especially on ARM, is completely under SW control. > > > > There is nothing in the GIC spec that says that. > > > >> There is some commonly used IOVA base in Linux for the ITS page, but > >> no HW should hardwire that. > > > > That's not strictly true. It really depends on how this block is > > integrated, and there is a number of existing blocks that know *in HW* > > how to signal an LPI. > > > > See, as the canonical example, how the mbigen driver doesn't need to > > know about the address of GITS_TRANSLATER. > > > > Yes, this messes with translation (the access is downstream of the > > SMMU) if you relied on it to have some isolation, and it has a "black > > hole" effect as nobody can have an IOVA that overlaps with the > > physical address of the GITS_TRANSLATER register. > > > > But is it illegal as per the architecture? No. It's just stupid. > > If that were the case, then we'd also need a platform quirk so the > SMMU driver knows about it. Yuck. Yup. As I said, this is stupid. > But even then, are you suggesting there is some way to convince the > ITS driver to allocate a specific predetermined EventID when a driver > requests an MSI? Asking for a friend... Of course not. Whoever did that has decided to hardcode the Linux behaviour into the HW, because it is well known that SW behaviour never changes. Nononono. I am >this< tempted to sneak a change into the allocation scheme to start at 5 or 13 (alternatively), and to map LPIs top-down. That should get people thinking. Cheers, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel