Re: [QUERY]: Acknowledgment of edge triggered interrupts

[Marc Zyngier <maz@kernel.org>]

On Sat, 30 Apr 2022 19:41:24 +0100,
"Lad, Prabhakar" <prabhakar.csengg@gmail.com> wrote:
> 
> Hi Marc,
> 
> I am currently working on the irq-sifive-plic.c driver. The
> irq-sifive-plic.c driver is currently implemented as a chained domain.
> On our SoC which uses this block for EDGE interrupts we need to first
> acknowledge the interrupt before handling it.

Isn't that what the CLAIM register does on the PLIC? AFAICT, this
interrupt controller is able to implement the whole flow, irrespective
of the trigger mechanism.

The spec strongly hints at that, see [1] ("Interrupt gateways"), and
the uniform handling that results of it. In a way, this is strikingly
similar to what the original ARM GIC does.

[1] https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc

> 
> I came across a similar situation on a different driver (patch [0])
> but it isn't a chained handler.
> 
> What approach should be taken for chained IRQ domains to handle such cases?

I don't think there is anything to change. At least, as long as the
Interrupt Gateway is doing its job correctly. How this gateway is
configured is unfortunately out of the scope of the architecture, it
seems, and I'd expect your HW to have some sort of knobs for the
trigger type to be configured. This would be dealt with in a separate
stacked driver.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

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