From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDCAFC4338F for ; Fri, 20 Aug 2021 13:57:47 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A2BC061051 for ; Fri, 20 Aug 2021 13:57:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org A2BC061051 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Subject:Cc:To:From:Message-ID:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=wCgoaysuJLWM4PVpy9pc9O9nxbPr2vED6xB1epr3Rco=; b=3RxyCeAEgklKoz ZGMC2ZzkxcvCR+DsRwMcJd5IWu8kWO3oHmiwhnWTOlpbdX38wPx5qFTpQxkLtBuDsacjoK7MPPfGV ysoiSaCV+2CxR11Fst8p2lEKYpZT/pqZd14qk3wy8GxW7a/AWbzTfFycwD6kFA0jov8nMLhFi6lak eMr8wkeLQNhiNw3OtT3aZ9O2uuDR1mA27KaTw5XusqCoEYl/tYxlWg/ZoLNFlTiUjAZ/B/6/d+kvq 4lMfrlZpYmo+XtfKxLPScg4iEE742v0yyimlAIqBVIyvjPqzFTenpsE+d2qMkrOsuAnh+3t3gGUKl zX+fNzvhQiPg6ZFj3M3g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mH4zZ-00BLDc-7e; Fri, 20 Aug 2021 13:55:29 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mH4zT-00BLCK-3Z for linux-arm-kernel@lists.infradead.org; Fri, 20 Aug 2021 13:55:27 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id A93C661075; Fri, 20 Aug 2021 13:55:22 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mH4zQ-006CSZ-Pu; Fri, 20 Aug 2021 14:55:20 +0100 Date: Fri, 20 Aug 2021 14:55:20 +0100 Message-ID: <87mtpcqkzb.wl-maz@kernel.org> From: Marc Zyngier To: Alexandru Elisei Cc: Chen-Yu Tsai , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] irqchip/gic-v3: Fix priority comparison when non-secure priorities are used In-Reply-To: References: <20210811171505.1502090-1-wenst@chromium.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: alexandru.elisei@arm.com, wenst@chromium.org, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210820_065523_218435_C20D9355 X-CRM114-Status: GOOD ( 37.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 20 Aug 2021 14:31:39 +0100, Alexandru Elisei wrote: > > Hello, > > Pending Marc's testing (I realized I don't have any hardware to test > this on at the moment), this patch looks correct to me. One comment > below. Seems good so far. I tested it both in a VM, on a FIQ==1 host, and on D05, which runs with FIQ==0. Can't be more broken than it was... ;-) > > On 8/11/21 6:15 PM, Chen-Yu Tsai wrote: > > When non-secure priorities are used, compared to the raw priority set, > > the value read back from RPR is also right-shifted by one and the > > highest bit set. > > > > Add a macro to do the modifications to the raw priority when doing the > > comparison against the RPR value. This corrects the pseudo-NMI behavior > > when non-secure priorities in the GIC are used. Tested on 5.10 with > > the "IPI as pseudo-NMI" series [1] applied on MT8195. > > > > [1] https://lore.kernel.org/linux-arm-kernel/1604317487-14543-1-git-send-email-sumit.garg@linaro.org/ > > > > Fixes: 336780590990 ("irqchip/gic-v3: Support pseudo-NMIs when SCR_EL3.FIQ == 0") > > Signed-off-by: Chen-Yu Tsai > > --- > > drivers/irqchip/irq-gic-v3.c | 11 ++++++++++- > > 1 file changed, 10 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > > index e0f4debe64e1..e7a0b55413db 100644 > > --- a/drivers/irqchip/irq-gic-v3.c > > +++ b/drivers/irqchip/irq-gic-v3.c > > @@ -100,6 +100,15 @@ EXPORT_SYMBOL(gic_pmr_sync); > > DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities); > > EXPORT_SYMBOL(gic_nonsecure_priorities); > > > > +#define GICD_INT_RPR_PRI(priority) \ > > + ({ \ > > + u32 __priority = (priority); \ > > + if (static_branch_unlikely(&gic_nonsecure_priorities)) \ > > + __priority = 0x80 | (__priority >> 1); \ > > + \ > > + __priority; \ > > + }) > > Would you mind adding a comment to the macro explaining why it's > needed? This behaviour is rather subtle and I'm hoping it will save > someone's time at some point in the future. I'm thinking something > like this (please ignore it if you can think of something better): > > When the Non-secure world has access to group 0 interrupts > (SCR_EL3.FIQ = 0), reading the ICC_RPR_EL1 register will return the > Distributor's view of the interrupt priority. When GIC security is > enabled (GICD_CTLR.DS = 0), the interrupt priority written by > software is moved to the Non-secure range by the Distributor. If > both are true (which is the situation where gic_nonsecure_priorities > gets enabled), then we need to shift down the priority programmed by > software if we want match it against the value returned from > ICC_RPR_EL1. > > With a comment added: > > Reviewed-by: Alexandru Elisei Let me fold this into the commit and push it out again. Thanks, M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel