From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 43D2DC4338F for ; Wed, 25 Aug 2021 11:28:39 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0D4B4610E8 for ; Wed, 25 Aug 2021 11:28:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 0D4B4610E8 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=tkos.co.il Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:In-reply-to: Date:Subject:Cc:To:From:References:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=R+qxRr9V0W9+lW9JZ/rH3zqKQNRdcH15w34TrTGeqzc=; b=XEmXDvGFGw2VK/ 6LpMue9cVda47Yw0BxPXy5M9tLSROKqfYroaivcdmGqan7VPb25jS0GoKpuaUshtwY+kBy78HAr1M q3MvTKrdJ/EVWln88QreJpCPJC/PBRDfUYXiAJQ3Lo6i7j8I9Zi1rZtpQzYaiG7Mm2M55zGnfHWOQ Ar0tJB4U/9uXpiJH+/bQi8CGLPAxsxHtrH7UjEyrCCO3c5+W3nsYY6ACEyesTpVcUcVrOdGrEm4pi 9qqZCox0XNbEdj09P6zSRP3bQjp4kRTneGuiprIhILBKu59IeXVurG5THkie/AEJ/wpjp260UDUkb +oIhcVVzn7ECQ2L17CWQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mIr2Q-006oh0-HZ; Wed, 25 Aug 2021 11:25:46 +0000 Received: from guitar.tcltek.co.il ([192.115.133.116] helo=mx.tkos.co.il) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mIr2J-006oeA-CK; Wed, 25 Aug 2021 11:25:43 +0000 Received: from tarshish (unknown [10.0.8.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx.tkos.co.il (Postfix) with ESMTPS id D860E440E17; Wed, 25 Aug 2021 14:25:28 +0300 (IDT) References: User-agent: mu4e 1.6.3; emacs 27.1 From: Baruch Siach To: Rob Herring Cc: Andy Gross , Bjorn Andersson , Selvam Sathappan Periakaruppan , Kathiravan T , Bjorn Helgaas , Kishon Vijay Abraham I , Vinod Koul , Thierry Reding , Jonathan Hunter , Jingoo Han , Gustavo Pimentel , Robert Marko , devicetree@vger.kernel.org, linux-phy@lists.infradead.org, PCI , linux-arm-msm , linux-arm-kernel , linux-tegra Subject: Re: [PATCH v2 2/6] PCI: qcom: add support for IPQ60xx PCIe controller Date: Wed, 25 Aug 2021 14:15:38 +0300 In-reply-to: Message-ID: <87o89lahqp.fsf@tarshish> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210825_042539_984591_47F62D5C X-CRM114-Status: GOOD ( 21.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Rob, On Fri, Aug 06 2021, Rob Herring wrote: > On Wed, May 5, 2021 at 3:18 AM Baruch Siach wrote: >> >> From: Selvam Sathappan Periakaruppan >> >> IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that >> platform. >> >> The code is based on downstream Codeaurora kernel v5.4. Split out the >> DBI registers access part from .init into .post_init. DBI registers are >> only accessible after phy_power_on(). >> >> Signed-off-by: Selvam Sathappan Periakaruppan >> Signed-off-by: Baruch Siach >> --- >> v2: >> * Drop ATU configuration; rely on common code instead >> >> * Use more common register macros >> >> * Use bulk clk and reset APIs >> --- >> drivers/pci/controller/dwc/pcie-designware.h | 1 + >> drivers/pci/controller/dwc/pcie-qcom.c | 150 +++++++++++++++++++ >> 2 files changed, 151 insertions(+) >> >> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h >> index ceb359b6e6a6..346462c74a3e 100644 >> --- a/drivers/pci/controller/dwc/pcie-designware.h >> +++ b/drivers/pci/controller/dwc/pcie-designware.h >> @@ -76,6 +76,7 @@ >> >> #define GEN3_RELATED_OFF 0x890 >> #define GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL BIT(0) >> +#define GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS BIT(13) >> #define GEN3_RELATED_OFF_GEN3_EQ_DISABLE BIT(16) >> #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT 24 >> #define GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK GENMASK(25, 24) >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c >> index 8a7a300163e5..93766aee3e7c 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >> @@ -52,6 +52,10 @@ >> #define PCIE20_PARF_DBI_BASE_ADDR 0x168 >> #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C >> #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 >> +#define AHB_CLK_EN BIT(0) >> +#define MSTR_AXI_CLK_EN BIT(1) >> +#define BYPASS BIT(4) >> + >> #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178 >> #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1A8 >> #define PCIE20_PARF_LTSSM 0x1B0 >> @@ -94,6 +98,12 @@ >> #define SLV_ADDR_SPACE_SZ 0x10000000 >> >> #define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0 >> +#define PCIE_CAP_CURR_DEEMPHASIS BIT(16) > > Isn't this a standard register field? I don't know. I could not find any reference to this field or the registers it's part of. n >> +#define SPEED_GEN1 0x1 >> +#define SPEED_GEN2 0x2 >> +#define SPEED_GEN3 0x3 > > And these? > > There's already some common DWC code for setting the link speed. dw_pcie_link_set_max_speed() deals with other registers, as far as I can see. >> +#define AXI_CLK_RATE 200000000 >> +#define RCHNG_CLK_RATE 100000000 >> >> #define DEVICE_TYPE_RC 0x4 [snip] >> +static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) >> +{ >> + struct dw_pcie *pci = pcie->pci; >> + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); >> + u32 val; >> + int i; >> + >> + writel(SLV_ADDR_SPACE_SZ, >> + pcie->parf + PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE); >> + >> + val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); >> + val &= ~BIT(0); >> + writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); >> + >> + writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR); >> + >> + writel(DEVICE_TYPE_RC, pcie->parf + PCIE20_PARF_DEVICE_TYPE); >> + writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN, >> + pcie->parf + PCIE20_PARF_MHI_CLOCK_RESET_CTRL); >> + writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS >> + | GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL, >> + pci->dbi_base + GEN3_RELATED_OFF); >> + >> + writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS >> + | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS | >> + AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS, >> + pcie->parf + PCIE20_PARF_SYS_CTRL); >> + >> + writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH); >> + >> + dw_pcie_dbi_ro_wr_en(pci); >> + writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); >> + >> + /* Configure PCIe link capabilities for ASPM */ >> + val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); >> + val &= ~PCI_EXP_LNKCAP_ASPMS; >> + writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); >> + >> + writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + >> + PCI_EXP_DEVCTL2); >> + >> + writel(PCIE_CAP_CURR_DEEMPHASIS | SPEED_GEN3, >> + pci->dbi_base + offset + PCI_EXP_DEVCTL2); > > Doesn't this overwrite the prior register write? It does. There are two mistakes here. The writel() above should set PCIE20_DEVICE_CONTROL2_STATUS2 (offset 0x98). This writel() should set PCIE20_LNK_CONTROL2_LINK_STATUS2 (offset 0xa0). So both are wrong. >> + >> + for (i = 0;i < 256;i++) >> + writel(0x0, pcie->parf + PCIE20_PARF_BDF_TO_SID_TABLE_N >> + + (4 * i)); >> + >> + return 0; >> +} Thanks, baruch -- ~. .~ Tk Open Systems =}------------------------------------------------ooO--U--Ooo------------{= - baruch@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il - _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel