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Thu, 21 Feb 2019 08:20:39 -0800 (PST) Received: from localhost.localdomain ([182.69.202.151]) by smtp.gmail.com with ESMTPSA id 63sm16192391pfs.65.2019.02.21.08.20.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Feb 2019 08:20:38 -0800 (PST) Subject: Re: [PATCH] arm64, vmcoreinfo : Append 'MAX_USER_VA_BITS' and 'MAX_PHYSMEM_BITS' to vmcoreinfo To: Kazuhito Hagio References: <1548850991-11879-1-git-send-email-bhsharma@redhat.com> <20190131014800.GB15785@dhcp-128-65.nay.redhat.com> <4AE2DC15AC0B8543882A74EA0D43DBEC03567AA3@BPXM09GP.gisp.nec.co.jp> <20190212104407.GA17022@dhcp-128-65.nay.redhat.com> <4AE2DC15AC0B8543882A74EA0D43DBEC035683DB@BPXM09GP.gisp.nec.co.jp> <20190213111552.GA8265@dhcp-128-65.nay.redhat.com> <4AE2DC15AC0B8543882A74EA0D43DBEC03568504@BPXM09GP.gisp.nec.co.jp> <37ed4c14-e4b9-49c0-4816-c289ce65fd76@arm.com> <4AE2DC15AC0B8543882A74EA0D43DBEC03568A9F@BPXM09GP.gisp.nec.co.jp> From: Bhupesh Sharma Message-ID: <891eaf5a-aede-364d-6465-832e377c3e29@redhat.com> Date: Thu, 21 Feb 2019 21:50:30 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.2.1 MIME-Version: 1.0 In-Reply-To: <4AE2DC15AC0B8543882A74EA0D43DBEC03568A9F@BPXM09GP.gisp.nec.co.jp> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190221_082040_201182_9E61168E X-CRM114-Status: GOOD ( 20.25 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , "lijiang@redhat.com" , "bhe@redhat.com" , "ard.biesheuvel@linaro.org" , "catalin.marinas@arm.com" , Steve Capper , "kexec@lists.infradead.org" , Will Deacon , AKASHI Takahiro , James Morse , Kristina Martsenko , Borislav Petkov , "anderson@redhat.com" , Dave Young , "linux-arm-kernel@lists.infradead.org" Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Kazu, On 02/20/2019 02:17 AM, Kazuhito Hagio wrote: > Hi Bhupesh, > > -----Original Message----- >> I am not sure you got a chance to look at the two regression cases I >> reported here: >> >> >> Unfortunately the above suggestion doesn't provide any fix for >> ARMv8.2-LPA regression (see text under heading ' >> (1). Regression Case 1 (ARMv8.2-LPA enabled kernel)') > > As for MAX_PHYSMEM_BITS, I realized that ppc64 makedumpfile can detect > it because there is only one SECTION_SIZE_BITS for ppc64. I think we > can use the same way as set_ppc64_max_physmem_bits() does also for > arm64 for now. I'm going to write it for kernels not having > NUMBER(MAX_PHYSMEM_BITS) in vmcoreinfo. I see two drawbacks with the above approach: a). This means that other user-space tools like crash-utility would still be broken and would probably need to find MAX_PHYSMEM_BITS for arm64 via a similar (hack'ish ?) approach. b). I am looking at the makedumpfile code for 'MAX_PHYSMEM_BITS' determination for two archs as an example: ppc --- int set_ppc64_max_physmem_bits(void) { long array_len = ARRAY_LENGTH(mem_section); /* * The older ppc64 kernels uses _MAX_PHYSMEM_BITS as 42 and the * newer kernels 3.7 onwards uses 46 bits. */ info->max_physmem_bits = _MAX_PHYSMEM_BITS_ORIG ; if ((array_len == (NR_MEM_SECTIONS() / _SECTIONS_PER_ROOT_EXTREME())) || (array_len == (NR_MEM_SECTIONS() / _SECTIONS_PER_ROOT()))) return TRUE; info->max_physmem_bits = _MAX_PHYSMEM_BITS_3_7; if ((array_len == (NR_MEM_SECTIONS() / _SECTIONS_PER_ROOT_EXTREME())) || (array_len == (NR_MEM_SECTIONS() / _SECTIONS_PER_ROOT()))) return TRUE; info->max_physmem_bits = _MAX_PHYSMEM_BITS_4_19; if ((array_len == (NR_MEM_SECTIONS() / _SECTIONS_PER_ROOT_EXTREME())) || (array_len == (NR_MEM_SECTIONS() / _SECTIONS_PER_ROOT()))) return TRUE; info->max_physmem_bits = _MAX_PHYSMEM_BITS_4_20; if ((array_len == (NR_MEM_SECTIONS() / _SECTIONS_PER_ROOT_EXTREME())) || (array_len == (NR_MEM_SECTIONS() / _SECTIONS_PER_ROOT()))) return TRUE; return FALSE; } x86_64: ------ int get_versiondep_info_x86_64(void) { /* * On linux-2.6.26, MAX_PHYSMEM_BITS is changed to 44 from 40. */ if (info->kernel_version < KERNEL_VERSION(2, 6, 26)) info->max_physmem_bits = _MAX_PHYSMEM_BITS_ORIG; else if (info->kernel_version < KERNEL_VERSION(2, 6, 31)) info->max_physmem_bits = _MAX_PHYSMEM_BITS_2_6_26; else if(check_5level_paging()) info->max_physmem_bits = _MAX_PHYSMEM_BITS_5LEVEL; else info->max_physmem_bits = _MAX_PHYSMEM_BITS_2_6_31; ... } Looking at the above, two questions come to my mind: - Do we really need all the above complexity in user-space code, to hoop across various kernel versions and perform allocations for something that can be so easily exported via vmcoreinfo? Also we need to see how portable is the above code for a new kernel version - IMO, it will need another fix patch when we update to a new kernel version in near future. - Also do we need to replicate the above implementations across user-space tools when they can also utilize the vmcoreinfo information to determine the PA_BITS range without any additional arch/kernel version specific details as the single point of obtaining this information from the kernel? So, in view of the above, I would still advocate that we use a vmcoreinfo export for 'MAX_PHYSMEM_BITS' as well to have a uniform interface for the same across all user-land applications. Thanks, Bhupesh _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel