From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A63A9C433DF for ; Thu, 25 Jun 2020 16:25:52 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6DB74204EA for ; Thu, 25 Jun 2020 16:25:52 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="UC/91pHl" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6DB74204EA Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=qIutQbyD/PHv0iDCTx3wsG9spB5yl3f2QdRNJij0KJ8=; b=UC/91pHlllOSAnwN/mCsfEH5Q qqGMqFubxPJPG45bn8SEV5yJ33ZECxLMc9Np79kPK4DSM2/t/iKll/sdUXJyyZ/D7t4TNxVQnrdTM F0vIJtGf7/cs1bMtYQXm0En94V4hxJkdYvICfBd0DvxXsUAGFjFttUD1YNgFBfJomnwzhuAPgzWc5 qPFo7974MxPpFwsS2WRUBtf8bejwcDFs7yrr71GkJ2g4GPsigb7UOSHo1ZsUiyuO1w58HdX4vWUb4 pGvJjRoc90gE7rRp3zxUJv/bozkTMb4ZsPeWsWH+ExCUZa1T3sy3tFLhfqWECiigjA7BRCvYX9SDO rHF6qNv4A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1joUfY-00028q-Fu; Thu, 25 Jun 2020 16:24:08 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1joUfV-00028H-RM for linux-arm-kernel@lists.infradead.org; Thu, 25 Jun 2020 16:24:06 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 248191FB; Thu, 25 Jun 2020 09:24:05 -0700 (PDT) Received: from [192.168.0.110] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E75FA3F6CF; Thu, 25 Jun 2020 09:24:02 -0700 (PDT) Subject: Re: [PATCH v2 04/17] arm64: Add level-hinted TLB invalidation helper To: Marc Zyngier , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org References: <20200615132719.1932408-1-maz@kernel.org> <20200615132719.1932408-5-maz@kernel.org> From: Alexandru Elisei Message-ID: <89d18c52-f3ee-8286-9353-1cd28226984a@arm.com> Date: Thu, 25 Jun 2020 17:24:31 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.9.0 MIME-Version: 1.0 In-Reply-To: <20200615132719.1932408-5-maz@kernel.org> Content-Language: en-US X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , kernel-team@android.com, Suzuki K Poulose , Andre Przywara , Christoffer Dall , Dave Martin , George Cherian , James Morse , Andrew Scull , "Zengtao \(B\)" , Catalin Marinas , Will Deacon , Jintack Lim , Julien Thierry Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, On 6/15/20 2:27 PM, Marc Zyngier wrote: > Add a level-hinted TLB invalidation helper that only gets used if > ARMv8.4-TTL gets detected. > > Signed-off-by: Marc Zyngier > --- > arch/arm64/include/asm/stage2_pgtable.h | 9 +++++ > arch/arm64/include/asm/tlbflush.h | 45 +++++++++++++++++++++++++ > 2 files changed, 54 insertions(+) > > diff --git a/arch/arm64/include/asm/stage2_pgtable.h b/arch/arm64/include/asm/stage2_pgtable.h > index b767904f28b1..996bf98f0cab 100644 > --- a/arch/arm64/include/asm/stage2_pgtable.h > +++ b/arch/arm64/include/asm/stage2_pgtable.h > @@ -256,4 +256,13 @@ stage2_pgd_addr_end(struct kvm *kvm, phys_addr_t addr, phys_addr_t end) > return (boundary - 1 < end - 1) ? boundary : end; > } > > +/* > + * Level values for the ARMv8.4-TTL extension, mapping PUD/PMD/PTE and > + * the architectural page-table level. > + */ > +#define S2_NO_LEVEL_HINT 0 > +#define S2_PUD_LEVEL 1 > +#define S2_PMD_LEVEL 2 > +#define S2_PTE_LEVEL 3 > + > #endif /* __ARM64_S2_PGTABLE_H_ */ > diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h > index bc3949064725..e05c31fd0bbc 100644 > --- a/arch/arm64/include/asm/tlbflush.h > +++ b/arch/arm64/include/asm/tlbflush.h > @@ -10,6 +10,7 @@ > > #ifndef __ASSEMBLY__ > > +#include > #include > #include > #include > @@ -59,6 +60,50 @@ > __ta; \ > }) > > +/* > + * Level-based TLBI operations. > + * > + * When ARMv8.4-TTL exists, TLBI operations take an additional hint for > + * the level at which the invalidation must take place. If the level is > + * wrong, no invalidation may take place. In the case where the level > + * cannot be easily determined, a 0 value for the level parameter will > + * perform a non-hinted invalidation. > + * > + * For Stage-2 invalidation, use the level values provided to that effect > + * in asm/stage2_pgtable.h. > + */ > +#define TLBI_TTL_MASK GENMASK_ULL(47, 44) > +#define TLBI_TTL_PS_4K 1 > +#define TLBI_TTL_PS_16K 2 > +#define TLBI_TTL_PS_64K 3 The Arm ARM likes to call those translation granules, so maybe we can use TG instead of PS to be aligned with the field names in TCR/VTCR? Just a suggestion in case you think it works better than PS, otherwise feel free to ignore it. > + > +#define __tlbi_level(op, addr, level) \ > + do { \ > + u64 arg = addr; \ > + \ > + if (cpus_have_const_cap(ARM64_HAS_ARMv8_4_TTL) && \ > + level) { \ > + u64 ttl = level & 3; \ > + \ > + switch (PAGE_SIZE) { \ > + case SZ_4K: \ > + ttl |= TLBI_TTL_PS_4K << 2; \ > + break; \ > + case SZ_16K: \ > + ttl |= TLBI_TTL_PS_16K << 2; \ > + break; \ > + case SZ_64K: \ > + ttl |= TLBI_TTL_PS_64K << 2; \ > + break; \ > + } \ > + \ > + arg &= ~TLBI_TTL_MASK; \ > + arg |= FIELD_PREP(TLBI_TTL_MASK, ttl); \ > + } \ > + \ > + __tlbi(op, arg); \ > + } while(0) > + > /* > * TLB Invalidation > * ================ I like the fact that defines are now used. I checked against Arm ARM, pages D5-2673 and D5-2674, and the granule size and the table level fields match, so: Reviewed-by: Alexandru Elisei Thanks, Alex _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel