From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A208DC3B1B5 for ; Fri, 14 Feb 2020 18:18:53 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 765C3222C2 for ; Fri, 14 Feb 2020 18:18:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="oKHgK0Qy" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 765C3222C2 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=GFOHC/UsaEZlZRpgzdq4zOxlo7jLRbnTZmOfVMERVQw=; b=oKHgK0QypPKzTpqdn+ayAGHvy r609EwpGL1bo1b+rGoTWr86/eH3Z9PEfFONGXkHejpuZElLQ1jztTOw4InRwSLfKOm4kXBPZEQ/IE jckbL+2o/wTTJi0w3r/WCDTFsvWr7gUij6F9Tex06/P6KOYx6YrHnBj9QzLM5yeoT8UVW/YtuINr9 +asFyDc3WPVGEfs9IIkXrBs6vkX4EhLw7qBcy4xig2UDvWzHWUMHJ3UXSFHot9B9SUCUMc5r08a/h mq+SfmB0TLGSnYk/QdBsx2ztlQ5ByXSZuSgHTUy9NENGlorH8ZvRvPVRGPiBMWWufeT/xEu30ouRA SY6WhrNrA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1j2fY7-0003Cj-Lx; Fri, 14 Feb 2020 18:18:47 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1j2fY5-0003Bx-6A for linux-arm-kernel@lists.infradead.org; Fri, 14 Feb 2020 18:18:46 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 67607328; Fri, 14 Feb 2020 10:18:44 -0800 (PST) Received: from [10.1.196.37] (e121345-lin.cambridge.arm.com [10.1.196.37]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 731B43F68E; Fri, 14 Feb 2020 10:18:43 -0800 (PST) Subject: Re: [PATCH 1/2] arm64: dts: allwinner: h5: Fix PMU compatible To: Andre Przywara , Maxime Ripard , Mark Rutland , Rob Herring References: <20200210095600.77894-1-maxime@cerno.tech> <20200214180404.24d67f86@donnerap.cambridge.arm.com> From: Robin Murphy Message-ID: <8e9f3a0e-d803-77bf-8f0f-04a7f4a00687@arm.com> Date: Fri, 14 Feb 2020 18:18:41 +0000 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: <20200214180404.24d67f86@donnerap.cambridge.arm.com> Content-Language: en-GB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200214_101845_272113_0A26C86C X-CRM114-Status: GOOD ( 25.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chen-Yu Tsai , Maxime Ripard , linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 14/02/2020 6:04 pm, Andre Przywara wrote: > On Mon, 10 Feb 2020 10:55:59 +0100 > Maxime Ripard wrote: > > Hi, > >> The commit c35a516a4618 ("arm64: dts: allwinner: H5: Add PMU node") >> introduced support for the PMU found on the Allwinner H5. However, the >> binding only allows for a single compatible, while the patch was adding >> two. > > Maxime, thanks for bringing this up, was that found by some validation tool? > > And while this is true, I wonder if this was intentional? > I see several other combinations of PMU compatibles in the tree. > > Mark, Rob, can you shed any light on this? > > Actually I am wondering why we would need the PMU type in the first place, isn't that discoverable via the MIDR? "the" MIDR... ;) Usual big.LITTLE vs. CPU hotplug rules apply. > And all we actually need from the DT is the interrupts and maybe some quirk info? > > It looks like ACPI is always using the generic PMUv3 map, so wouldn't it actually be better to replace the compatible string matching with MIDR matching? Or are those core specific maps somewhat obsolete anyway? Since I don't see any newer cores in there? Mostly they're just long overdue for an update (and somewhat mitigated by the userspace JSON stuff in perf tools, but in principle there are still other users of perf_events). IIRC, the generic PMUv3 compatible was only ever meant to be for things like the AEM without a specific microarchitecture (cf. the "arm,armv8" CPU binding). Robin. > > Cheers, > Andre > >> Make sure we follow the binding. > > >> >> Fixes: c35a516a4618 ("arm64: dts: allwinner: H5: Add PMU node") >> Signed-off-by: Maxime Ripard >> --- >> arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 3 +-- >> 1 file changed, 1 insertion(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi >> index 9893aa64dd0b..4462a68c0681 100644 >> --- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi >> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi >> @@ -38,8 +38,7 @@ cpu3: cpu@3 { >> }; >> >> pmu { >> - compatible = "arm,cortex-a53-pmu", >> - "arm,armv8-pmuv3"; >> + compatible = "arm,cortex-a53-pmu"; >> interrupts = , >> , >> , > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel