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* [PATCH 0/3] iommu/io-pgtable-arm: Mali LPAE improvements
@ 2019-09-11 14:42 Robin Murphy
  2019-09-11 14:42 ` [PATCH 1/3] iommu/io-pgtable-arm: Correct Mali attributes Robin Murphy
                   ` (3 more replies)
  0 siblings, 4 replies; 11+ messages in thread
From: Robin Murphy @ 2019-09-11 14:42 UTC (permalink / raw)
  To: will, joro
  Cc: robh, tomeu.vizoso, narmstrong, steven.price, iommu, linux-arm-kernel

Hi all,

Here's the eagerly-awaited fix to unblock T720/T820, plus a couple of
other bits that I've collected so far. I'm not considering this as
5.3 fixes material, but it would be nice if there's any chance still
to sneak it into 5.4.

Robin.


Robin Murphy (3):
  iommu/io-pgtable-arm: Correct Mali attributes
  iommu/io-pgtable-arm: Support more Mali configurations
  iommu/io-pgtable-arm: Allow coherent walks for Mali

 drivers/iommu/io-pgtable-arm.c | 61 ++++++++++++++++++++++++++--------
 1 file changed, 48 insertions(+), 13 deletions(-)

-- 
2.21.0.dirty


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^ permalink raw reply	[flat|nested] 11+ messages in thread

* [PATCH 1/3] iommu/io-pgtable-arm: Correct Mali attributes
  2019-09-11 14:42 [PATCH 0/3] iommu/io-pgtable-arm: Mali LPAE improvements Robin Murphy
@ 2019-09-11 14:42 ` Robin Murphy
  2019-09-12 10:41   ` Steven Price
  2019-09-11 14:42 ` [PATCH 2/3] iommu/io-pgtable-arm: Support more Mali configurations Robin Murphy
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 11+ messages in thread
From: Robin Murphy @ 2019-09-11 14:42 UTC (permalink / raw)
  To: will, joro
  Cc: robh, tomeu.vizoso, narmstrong, steven.price, iommu, linux-arm-kernel

Whilst Midgard's MEMATTR follows a similar principle to the VMSA MAIR,
the actual attribute values differ, so although it currently appears to
work to some degree, we probably shouldn't be using our standard stage 1
MAIR for that. Instead, generate a reasonable MEMATTR with attribute
values borrowed from the kbase driver; at this point we'll be overriding
or ignoring pretty much all of the LPAE config, so just implement these
Mali details in a dedicated allocator instead of pretending to subclass
the standard VMSA format.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 drivers/iommu/io-pgtable-arm.c | 53 +++++++++++++++++++++++++---------
 1 file changed, 40 insertions(+), 13 deletions(-)

diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index 161a7d56264d..9e35cd991f06 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -167,6 +167,9 @@
 #define ARM_MALI_LPAE_TTBR_READ_INNER	BIT(2)
 #define ARM_MALI_LPAE_TTBR_SHARE_OUTER	BIT(4)
 
+#define ARM_MALI_LPAE_MEMATTR_IMP_DEF	0x88ULL
+#define ARM_MALI_LPAE_MEMATTR_WRITE_ALLOC 0x8DULL
+
 /* IOPTE accessors */
 #define iopte_deref(pte,d) __va(iopte_to_paddr(pte, d))
 
@@ -1013,27 +1016,51 @@ arm_32_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
 static struct io_pgtable *
 arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
 {
-	struct io_pgtable *iop;
+	struct arm_lpae_io_pgtable *data;
+
+	/* No quirks for Mali (hopefully) */
+	if (cfg->quirks)
+		return NULL;
 
 	if (cfg->ias != 48 || cfg->oas > 40)
 		return NULL;
 
 	cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
-	iop = arm_64_lpae_alloc_pgtable_s1(cfg, cookie);
-	if (iop) {
-		u64 mair, ttbr;
 
-		/* Copy values as union fields overlap */
-		mair = cfg->arm_lpae_s1_cfg.mair[0];
-		ttbr = cfg->arm_lpae_s1_cfg.ttbr[0];
+	data = arm_lpae_alloc_pgtable(cfg);
+	if (!data)
+		return NULL;
 
-		cfg->arm_mali_lpae_cfg.memattr = mair;
-		cfg->arm_mali_lpae_cfg.transtab = ttbr |
-			ARM_MALI_LPAE_TTBR_READ_INNER |
-			ARM_MALI_LPAE_TTBR_ADRMODE_TABLE;
-	}
+	/*
+	 * MEMATTR: Mali has no actual notion of a non-cacheable type, so the
+	 * best we can do is mimic the out-of-tree driver and hope that the
+	 * "implementation-defined caching policy" is good enough. Similarly,
+	 * we'll use it for the sake of a valid attribute for our 'device'
+	 * index, although callers should never request that in practice.
+	 */
+	cfg->arm_mali_lpae_cfg.memattr =
+		(ARM_MALI_LPAE_MEMATTR_IMP_DEF
+		 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_NC)) |
+		(ARM_MALI_LPAE_MEMATTR_WRITE_ALLOC
+		 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_CACHE)) |
+		(ARM_MALI_LPAE_MEMATTR_IMP_DEF
+		 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV));
 
-	return iop;
+	data->pgd = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg);
+	if (!data->pgd)
+		goto out_free_data;
+
+	/* Ensure the empty pgd is visible before TRANSTAB can be written */
+	wmb();
+
+	cfg->arm_mali_lpae_cfg.transtab = virt_to_phys(data->pgd) |
+					  ARM_MALI_LPAE_TTBR_READ_INNER |
+					  ARM_MALI_LPAE_TTBR_ADRMODE_TABLE;
+	return &data->iop;
+
+out_free_data:
+	kfree(data);
+	return NULL;
 }
 
 struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns = {
-- 
2.21.0.dirty


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^ permalink raw reply	[flat|nested] 11+ messages in thread

* [PATCH 2/3] iommu/io-pgtable-arm: Support more Mali configurations
  2019-09-11 14:42 [PATCH 0/3] iommu/io-pgtable-arm: Mali LPAE improvements Robin Murphy
  2019-09-11 14:42 ` [PATCH 1/3] iommu/io-pgtable-arm: Correct Mali attributes Robin Murphy
@ 2019-09-11 14:42 ` Robin Murphy
  2019-09-12 10:47   ` Steven Price
  2019-09-11 14:42 ` [PATCH 3/3] iommu/io-pgtable-arm: Allow coherent walks for Mali Robin Murphy
  2019-09-11 16:19 ` [PATCH 0/3] iommu/io-pgtable-arm: Mali LPAE improvements Neil Armstrong
  3 siblings, 1 reply; 11+ messages in thread
From: Robin Murphy @ 2019-09-11 14:42 UTC (permalink / raw)
  To: will, joro
  Cc: robh, tomeu.vizoso, narmstrong, steven.price, iommu, linux-arm-kernel

In principle, Midgard GPUs supporting smaller VA sizes should only
require 3-level pagetables, since the address bits resolved at level 0
(47:40) will never change. However, the kbase driver does not appear to
have any notion of a variable start level, and empirically T720 and T820
rapidly blow up with translation faults unless given a full 4-level
table, despite only supporting a 33-bit VA size.

The 'real' IAS value is still valuable in terms of validating addresses
on map/unmap, so tweak the allocator to allow smaller values while still
forcing the resultant tables to the full 4 levels.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 drivers/iommu/io-pgtable-arm.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index 9e35cd991f06..77f41c9dd9be 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -1022,7 +1022,7 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
 	if (cfg->quirks)
 		return NULL;
 
-	if (cfg->ias != 48 || cfg->oas > 40)
+	if (cfg->ias > 48 || cfg->oas > 40)
 		return NULL;
 
 	cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
@@ -1031,6 +1031,11 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
 	if (!data)
 		return NULL;
 
+	/* Mali seems to need a full 4-level table regardless of IAS */
+	if (data->levels < ARM_LPAE_MAX_LEVELS) {
+		data->levels = ARM_LPAE_MAX_LEVELS;
+		data->pgd_size = sizeof(arm_lpae_iopte);
+	}
 	/*
 	 * MEMATTR: Mali has no actual notion of a non-cacheable type, so the
 	 * best we can do is mimic the out-of-tree driver and hope that the
-- 
2.21.0.dirty


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 11+ messages in thread

* [PATCH 3/3] iommu/io-pgtable-arm: Allow coherent walks for Mali
  2019-09-11 14:42 [PATCH 0/3] iommu/io-pgtable-arm: Mali LPAE improvements Robin Murphy
  2019-09-11 14:42 ` [PATCH 1/3] iommu/io-pgtable-arm: Correct Mali attributes Robin Murphy
  2019-09-11 14:42 ` [PATCH 2/3] iommu/io-pgtable-arm: Support more Mali configurations Robin Murphy
@ 2019-09-11 14:42 ` Robin Murphy
  2019-09-12 10:53   ` Steven Price
  2019-09-11 16:19 ` [PATCH 0/3] iommu/io-pgtable-arm: Mali LPAE improvements Neil Armstrong
  3 siblings, 1 reply; 11+ messages in thread
From: Robin Murphy @ 2019-09-11 14:42 UTC (permalink / raw)
  To: will, joro
  Cc: robh, tomeu.vizoso, narmstrong, steven.price, iommu, linux-arm-kernel

Midgard GPUs have ACE-Lite master interfaces which allows systems to
integrate them in an I/O-coherent manner. It seems that from the GPU's
viewpoint, the rest of the system is its outer shareable domain, and it
will only emit snoop signals for outer shareable accesses. As such,
setting the TTBR_SHARE_OUTER bit does indeed get coherent pagetable
walks working nicely.

Making data accesses coherent seems to be more of a challenge...

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 drivers/iommu/io-pgtable-arm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index 77f41c9dd9be..2794d4661339 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -1061,6 +1061,9 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
 	cfg->arm_mali_lpae_cfg.transtab = virt_to_phys(data->pgd) |
 					  ARM_MALI_LPAE_TTBR_READ_INNER |
 					  ARM_MALI_LPAE_TTBR_ADRMODE_TABLE;
+	if (cfg->coherent_walk)
+		cfg->arm_mali_lpae_cfg.transtab |= ARM_MALI_LPAE_TTBR_SHARE_OUTER;
+
 	return &data->iop;
 
 out_free_data:
-- 
2.21.0.dirty


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^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH 0/3] iommu/io-pgtable-arm: Mali LPAE improvements
  2019-09-11 14:42 [PATCH 0/3] iommu/io-pgtable-arm: Mali LPAE improvements Robin Murphy
                   ` (2 preceding siblings ...)
  2019-09-11 14:42 ` [PATCH 3/3] iommu/io-pgtable-arm: Allow coherent walks for Mali Robin Murphy
@ 2019-09-11 16:19 ` Neil Armstrong
  2019-09-11 16:20   ` Will Deacon
  3 siblings, 1 reply; 11+ messages in thread
From: Neil Armstrong @ 2019-09-11 16:19 UTC (permalink / raw)
  To: Robin Murphy, will, joro
  Cc: robh, iommu, tomeu.vizoso, linux-arm-kernel, steven.price

Hi,

On 11/09/2019 16:42, Robin Murphy wrote:
> Hi all,
> 
> Here's the eagerly-awaited fix to unblock T720/T820, plus a couple of
> other bits that I've collected so far. I'm not considering this as
> 5.3 fixes material, but it would be nice if there's any chance still
> to sneak it into 5.4.
> 
> Robin.
> 
> 
> Robin Murphy (3):
>   iommu/io-pgtable-arm: Correct Mali attributes
>   iommu/io-pgtable-arm: Support more Mali configurations
>   iommu/io-pgtable-arm: Allow coherent walks for Mali
> 
>  drivers/iommu/io-pgtable-arm.c | 61 ++++++++++++++++++++++++++--------
>  1 file changed, 48 insertions(+), 13 deletions(-)
> 

Tested-by: Neil Armstrong <narmstrong@baylibre.com>

On Khadas VIM2 (Amlogic S912) with T820 Mali GPU

I hope this will be part of v5.4 so we can run panfrost on vanilla v5.4 !

Thanks for pushing this,
Neil

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^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH 0/3] iommu/io-pgtable-arm: Mali LPAE improvements
  2019-09-11 16:19 ` [PATCH 0/3] iommu/io-pgtable-arm: Mali LPAE improvements Neil Armstrong
@ 2019-09-11 16:20   ` Will Deacon
  2019-09-11 17:19     ` Robin Murphy
  0 siblings, 1 reply; 11+ messages in thread
From: Will Deacon @ 2019-09-11 16:20 UTC (permalink / raw)
  To: Neil Armstrong
  Cc: robh, tomeu.vizoso, joro, steven.price, iommu, Robin Murphy,
	linux-arm-kernel

On Wed, Sep 11, 2019 at 06:19:04PM +0200, Neil Armstrong wrote:
> On 11/09/2019 16:42, Robin Murphy wrote:
> > Here's the eagerly-awaited fix to unblock T720/T820, plus a couple of
> > other bits that I've collected so far. I'm not considering this as
> > 5.3 fixes material, but it would be nice if there's any chance still
> > to sneak it into 5.4.
> > 
> > Robin.
> > 
> > 
> > Robin Murphy (3):
> >   iommu/io-pgtable-arm: Correct Mali attributes
> >   iommu/io-pgtable-arm: Support more Mali configurations
> >   iommu/io-pgtable-arm: Allow coherent walks for Mali
> > 
> >  drivers/iommu/io-pgtable-arm.c | 61 ++++++++++++++++++++++++++--------
> >  1 file changed, 48 insertions(+), 13 deletions(-)
> > 
> 
> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
> 
> On Khadas VIM2 (Amlogic S912) with T820 Mali GPU
> 
> I hope this will be part of v5.4 so we can run panfrost on vanilla v5.4 !

Not a chance -- the merge window opens on Monday and -next isn't being
rolled out at the moment due to LPC. Let's shoot for 5.5 and get this
queued up in a few weeks.

Will

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^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH 0/3] iommu/io-pgtable-arm: Mali LPAE improvements
  2019-09-11 16:20   ` Will Deacon
@ 2019-09-11 17:19     ` Robin Murphy
  2019-09-19  8:30       ` Will Deacon
  0 siblings, 1 reply; 11+ messages in thread
From: Robin Murphy @ 2019-09-11 17:19 UTC (permalink / raw)
  To: Will Deacon, Neil Armstrong
  Cc: robh, tomeu.vizoso, joro, steven.price, iommu, linux-arm-kernel

On 2019-09-11 5:20 pm, Will Deacon wrote:
> On Wed, Sep 11, 2019 at 06:19:04PM +0200, Neil Armstrong wrote:
>> On 11/09/2019 16:42, Robin Murphy wrote:
>>> Here's the eagerly-awaited fix to unblock T720/T820, plus a couple of
>>> other bits that I've collected so far. I'm not considering this as
>>> 5.3 fixes material, but it would be nice if there's any chance still
>>> to sneak it into 5.4.
>>>
>>> Robin.
>>>
>>>
>>> Robin Murphy (3):
>>>    iommu/io-pgtable-arm: Correct Mali attributes
>>>    iommu/io-pgtable-arm: Support more Mali configurations
>>>    iommu/io-pgtable-arm: Allow coherent walks for Mali
>>>
>>>   drivers/iommu/io-pgtable-arm.c | 61 ++++++++++++++++++++++++++--------
>>>   1 file changed, 48 insertions(+), 13 deletions(-)
>>>
>>
>> Tested-by: Neil Armstrong <narmstrong@baylibre.com>
>>
>> On Khadas VIM2 (Amlogic S912) with T820 Mali GPU
>>
>> I hope this will be part of v5.4 so we can run panfrost on vanilla v5.4 !
> 
> Not a chance -- the merge window opens on Monday and -next isn't being
> rolled out at the moment due to LPC. Let's shoot for 5.5 and get this
> queued up in a few weeks.

Fair enough, that was certainly more extreme optimism than realistic 
expectation on my part :)

There is some argument for taking #1 and #2 as 5.4 fixes, though - the 
upcoming Mesa 19.2 release will enable T820 support on the userspace 
side - so let's pick that discussion up again in a few weeks.

Robin.

(And at worst, I guess we could carry the "cfg.ias = 48" workaround in 
the DRM driver for the 5.4 cycle if need be)

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^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH 1/3] iommu/io-pgtable-arm: Correct Mali attributes
  2019-09-11 14:42 ` [PATCH 1/3] iommu/io-pgtable-arm: Correct Mali attributes Robin Murphy
@ 2019-09-12 10:41   ` Steven Price
  0 siblings, 0 replies; 11+ messages in thread
From: Steven Price @ 2019-09-12 10:41 UTC (permalink / raw)
  To: Robin Murphy, will, joro
  Cc: robh, iommu, linux-arm-kernel, tomeu.vizoso, narmstrong

On 11/09/2019 15:42, Robin Murphy wrote:
> Whilst Midgard's MEMATTR follows a similar principle to the VMSA MAIR,
> the actual attribute values differ, so although it currently appears to
> work to some degree, we probably shouldn't be using our standard stage 1
> MAIR for that. Instead, generate a reasonable MEMATTR with attribute
> values borrowed from the kbase driver; at this point we'll be overriding
> or ignoring pretty much all of the LPAE config, so just implement these
> Mali details in a dedicated allocator instead of pretending to subclass
> the standard VMSA format.
> 
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>

The Midgard MMU "uses concepts" from LPAE but really isn't LPAE, so this
seems like a good tidy up.

Reviewed-by: Steven Price <steven.price@arm.com>

Steve

> ---
>  drivers/iommu/io-pgtable-arm.c | 53 +++++++++++++++++++++++++---------
>  1 file changed, 40 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
> index 161a7d56264d..9e35cd991f06 100644
> --- a/drivers/iommu/io-pgtable-arm.c
> +++ b/drivers/iommu/io-pgtable-arm.c
> @@ -167,6 +167,9 @@
>  #define ARM_MALI_LPAE_TTBR_READ_INNER	BIT(2)
>  #define ARM_MALI_LPAE_TTBR_SHARE_OUTER	BIT(4)
>  
> +#define ARM_MALI_LPAE_MEMATTR_IMP_DEF	0x88ULL
> +#define ARM_MALI_LPAE_MEMATTR_WRITE_ALLOC 0x8DULL
> +
>  /* IOPTE accessors */
>  #define iopte_deref(pte,d) __va(iopte_to_paddr(pte, d))
>  
> @@ -1013,27 +1016,51 @@ arm_32_lpae_alloc_pgtable_s2(struct io_pgtable_cfg *cfg, void *cookie)
>  static struct io_pgtable *
>  arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
>  {
> -	struct io_pgtable *iop;
> +	struct arm_lpae_io_pgtable *data;
> +
> +	/* No quirks for Mali (hopefully) */
> +	if (cfg->quirks)
> +		return NULL;
>  
>  	if (cfg->ias != 48 || cfg->oas > 40)
>  		return NULL;
>  
>  	cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
> -	iop = arm_64_lpae_alloc_pgtable_s1(cfg, cookie);
> -	if (iop) {
> -		u64 mair, ttbr;
>  
> -		/* Copy values as union fields overlap */
> -		mair = cfg->arm_lpae_s1_cfg.mair[0];
> -		ttbr = cfg->arm_lpae_s1_cfg.ttbr[0];
> +	data = arm_lpae_alloc_pgtable(cfg);
> +	if (!data)
> +		return NULL;
>  
> -		cfg->arm_mali_lpae_cfg.memattr = mair;
> -		cfg->arm_mali_lpae_cfg.transtab = ttbr |
> -			ARM_MALI_LPAE_TTBR_READ_INNER |
> -			ARM_MALI_LPAE_TTBR_ADRMODE_TABLE;
> -	}
> +	/*
> +	 * MEMATTR: Mali has no actual notion of a non-cacheable type, so the
> +	 * best we can do is mimic the out-of-tree driver and hope that the
> +	 * "implementation-defined caching policy" is good enough. Similarly,
> +	 * we'll use it for the sake of a valid attribute for our 'device'
> +	 * index, although callers should never request that in practice.
> +	 */
> +	cfg->arm_mali_lpae_cfg.memattr =
> +		(ARM_MALI_LPAE_MEMATTR_IMP_DEF
> +		 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_NC)) |
> +		(ARM_MALI_LPAE_MEMATTR_WRITE_ALLOC
> +		 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_CACHE)) |
> +		(ARM_MALI_LPAE_MEMATTR_IMP_DEF
> +		 << ARM_LPAE_MAIR_ATTR_SHIFT(ARM_LPAE_MAIR_ATTR_IDX_DEV));
>  
> -	return iop;
> +	data->pgd = __arm_lpae_alloc_pages(data->pgd_size, GFP_KERNEL, cfg);
> +	if (!data->pgd)
> +		goto out_free_data;
> +
> +	/* Ensure the empty pgd is visible before TRANSTAB can be written */
> +	wmb();
> +
> +	cfg->arm_mali_lpae_cfg.transtab = virt_to_phys(data->pgd) |
> +					  ARM_MALI_LPAE_TTBR_READ_INNER |
> +					  ARM_MALI_LPAE_TTBR_ADRMODE_TABLE;
> +	return &data->iop;
> +
> +out_free_data:
> +	kfree(data);
> +	return NULL;
>  }
>  
>  struct io_pgtable_init_fns io_pgtable_arm_64_lpae_s1_init_fns = {
> 


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^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH 2/3] iommu/io-pgtable-arm: Support more Mali configurations
  2019-09-11 14:42 ` [PATCH 2/3] iommu/io-pgtable-arm: Support more Mali configurations Robin Murphy
@ 2019-09-12 10:47   ` Steven Price
  0 siblings, 0 replies; 11+ messages in thread
From: Steven Price @ 2019-09-12 10:47 UTC (permalink / raw)
  To: Robin Murphy, will, joro
  Cc: robh, iommu, linux-arm-kernel, tomeu.vizoso, narmstrong

On 11/09/2019 15:42, Robin Murphy wrote:
> In principle, Midgard GPUs supporting smaller VA sizes should only
> require 3-level pagetables, since the address bits resolved at level 0
> (47:40) will never change. However, the kbase driver does not appear to
> have any notion of a variable start level, and empirically T720 and T820
> rapidly blow up with translation faults unless given a full 4-level
> table, despite only supporting a 33-bit VA size.

Midgard 'LPAE' isn't really LPAE and does indeed always require all
levels of page tables. The 33-bit VA size is really only limiting the
storage of virtual addresses in the GPU and not affecting the MMU.

> The 'real' IAS value is still valuable in terms of validating addresses
> on map/unmap, so tweak the allocator to allow smaller values while still
> forcing the resultant tables to the full 4 levels.
> 
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>

Reviewed-by: Steven Price <steven.price@arm.com>

Steve

> ---
>  drivers/iommu/io-pgtable-arm.c | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
> index 9e35cd991f06..77f41c9dd9be 100644
> --- a/drivers/iommu/io-pgtable-arm.c
> +++ b/drivers/iommu/io-pgtable-arm.c
> @@ -1022,7 +1022,7 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
>  	if (cfg->quirks)
>  		return NULL;
>  
> -	if (cfg->ias != 48 || cfg->oas > 40)
> +	if (cfg->ias > 48 || cfg->oas > 40)
>  		return NULL;
>  
>  	cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
> @@ -1031,6 +1031,11 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
>  	if (!data)
>  		return NULL;
>  
> +	/* Mali seems to need a full 4-level table regardless of IAS */
> +	if (data->levels < ARM_LPAE_MAX_LEVELS) {
> +		data->levels = ARM_LPAE_MAX_LEVELS;
> +		data->pgd_size = sizeof(arm_lpae_iopte);
> +	}
>  	/*
>  	 * MEMATTR: Mali has no actual notion of a non-cacheable type, so the
>  	 * best we can do is mimic the out-of-tree driver and hope that the
> 


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^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH 3/3] iommu/io-pgtable-arm: Allow coherent walks for Mali
  2019-09-11 14:42 ` [PATCH 3/3] iommu/io-pgtable-arm: Allow coherent walks for Mali Robin Murphy
@ 2019-09-12 10:53   ` Steven Price
  0 siblings, 0 replies; 11+ messages in thread
From: Steven Price @ 2019-09-12 10:53 UTC (permalink / raw)
  To: Robin Murphy, will, joro
  Cc: robh, iommu, linux-arm-kernel, tomeu.vizoso, narmstrong

On 11/09/2019 15:42, Robin Murphy wrote:
> Midgard GPUs have ACE-Lite master interfaces which allows systems to
> integrate them in an I/O-coherent manner. It seems that from the GPU's
> viewpoint, the rest of the system is its outer shareable domain, and it
> will only emit snoop signals for outer shareable accesses. As such,
> setting the TTBR_SHARE_OUTER bit does indeed get coherent pagetable
> walks working nicely.
> 
> Making data accesses coherent seems to be more of a challenge...
> 
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>

Reviewed-by: Steven Price <steven.price@arm.com>

Note the terminology in the GPU is *very* confusing here. Midgard refers
to the system's inner shareable domain as "outer shareable", and uses
"inner shareable" to mean purely within the GPU.

For data access kbase sets up a different default MEMATTR if ACE is
available:

	/* Set to implementation defined, outer caching */
	#define AS_MEMATTR_LPAE_OUTER_IMPL_DEF        0x88ull
[...]
	#define AS_MEMATTR_INDEX_DEFAULT_ACE           3
[...]
	/* Outer coherent, inner implementation defined policy */
	#define AS_MEMATTR_INDEX_OUTER_IMPL_DEF        3

Steve

> ---
>  drivers/iommu/io-pgtable-arm.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
> index 77f41c9dd9be..2794d4661339 100644
> --- a/drivers/iommu/io-pgtable-arm.c
> +++ b/drivers/iommu/io-pgtable-arm.c
> @@ -1061,6 +1061,9 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
>  	cfg->arm_mali_lpae_cfg.transtab = virt_to_phys(data->pgd) |
>  					  ARM_MALI_LPAE_TTBR_READ_INNER |
>  					  ARM_MALI_LPAE_TTBR_ADRMODE_TABLE;
> +	if (cfg->coherent_walk)
> +		cfg->arm_mali_lpae_cfg.transtab |= ARM_MALI_LPAE_TTBR_SHARE_OUTER;
> +
>  	return &data->iop;
>  
>  out_free_data:
> 


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^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH 0/3] iommu/io-pgtable-arm: Mali LPAE improvements
  2019-09-11 17:19     ` Robin Murphy
@ 2019-09-19  8:30       ` Will Deacon
  0 siblings, 0 replies; 11+ messages in thread
From: Will Deacon @ 2019-09-19  8:30 UTC (permalink / raw)
  To: Robin Murphy
  Cc: robh, tomeu.vizoso, Neil Armstrong, joro, steven.price, iommu,
	linux-arm-kernel

On Wed, Sep 11, 2019 at 06:19:40PM +0100, Robin Murphy wrote:
> On 2019-09-11 5:20 pm, Will Deacon wrote:
> > On Wed, Sep 11, 2019 at 06:19:04PM +0200, Neil Armstrong wrote:
> > > On 11/09/2019 16:42, Robin Murphy wrote:
> > > > Here's the eagerly-awaited fix to unblock T720/T820, plus a couple of
> > > > other bits that I've collected so far. I'm not considering this as
> > > > 5.3 fixes material, but it would be nice if there's any chance still
> > > > to sneak it into 5.4.
> > > > 
> > > > Robin.
> > > > 
> > > > 
> > > > Robin Murphy (3):
> > > >    iommu/io-pgtable-arm: Correct Mali attributes
> > > >    iommu/io-pgtable-arm: Support more Mali configurations
> > > >    iommu/io-pgtable-arm: Allow coherent walks for Mali
> > > > 
> > > >   drivers/iommu/io-pgtable-arm.c | 61 ++++++++++++++++++++++++++--------
> > > >   1 file changed, 48 insertions(+), 13 deletions(-)
> > > > 
> > > 
> > > Tested-by: Neil Armstrong <narmstrong@baylibre.com>
> > > 
> > > On Khadas VIM2 (Amlogic S912) with T820 Mali GPU
> > > 
> > > I hope this will be part of v5.4 so we can run panfrost on vanilla v5.4 !
> > 
> > Not a chance -- the merge window opens on Monday and -next isn't being
> > rolled out at the moment due to LPC. Let's shoot for 5.5 and get this
> > queued up in a few weeks.
> 
> Fair enough, that was certainly more extreme optimism than realistic
> expectation on my part :)
> 
> There is some argument for taking #1 and #2 as 5.4 fixes, though - the
> upcoming Mesa 19.2 release will enable T820 support on the userspace side -
> so let's pick that discussion up again in a few weeks.

Ok, I'll include those two in my fixes pull to Joerg at -rc1.

Will

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^ permalink raw reply	[flat|nested] 11+ messages in thread

end of thread, back to index

Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-09-11 14:42 [PATCH 0/3] iommu/io-pgtable-arm: Mali LPAE improvements Robin Murphy
2019-09-11 14:42 ` [PATCH 1/3] iommu/io-pgtable-arm: Correct Mali attributes Robin Murphy
2019-09-12 10:41   ` Steven Price
2019-09-11 14:42 ` [PATCH 2/3] iommu/io-pgtable-arm: Support more Mali configurations Robin Murphy
2019-09-12 10:47   ` Steven Price
2019-09-11 14:42 ` [PATCH 3/3] iommu/io-pgtable-arm: Allow coherent walks for Mali Robin Murphy
2019-09-12 10:53   ` Steven Price
2019-09-11 16:19 ` [PATCH 0/3] iommu/io-pgtable-arm: Mali LPAE improvements Neil Armstrong
2019-09-11 16:20   ` Will Deacon
2019-09-11 17:19     ` Robin Murphy
2019-09-19  8:30       ` Will Deacon

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