From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC0C8C5519F for ; Mon, 23 Nov 2020 02:44:36 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6577C2076B for ; Mon, 23 Nov 2020 02:44:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="fR8xhmno" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6577C2076B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=FIK0NXuMoLWKeIs9FNmrE/aQohncnMd0ShzW2jM1+Os=; b=fR8xhmnoRkAP1cwbIBdvMZzim Bt/deZTqGetOru1IaaxxHQPs1QgFmsepsAZ5XPI7nGdonbjxvwulxPoUHNjkv6JgtjjdfIQUKPAeC xTIHPqOsq06HkA7fh5zb0FUj80l763X0AVgpj5KC2cCrJkYGMozPJEw+tLuEdRqD+UFGhg6HSs5Da G9jWVrR7abpWt4mL1VNxfqxI/8RENKl/1c4aCA1tNBnsmqUsPAQvbbnfYSMMVFgUe7vwgeU5bQxWa W8608D3se3XdC+1YTof6l8j93XQVQPwluUI7Y2k/emNELz5GrHIPxhmI5vKv/VdhkyZ0fzEbYX6cW EO/soLmWw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kh1p4-0005Yk-Tc; Mon, 23 Nov 2020 02:43:22 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kh1p1-0005YK-QP for linux-arm-kernel@lists.infradead.org; Mon, 23 Nov 2020 02:43:20 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AB47730E; Sun, 22 Nov 2020 18:43:18 -0800 (PST) Received: from [10.163.82.200] (unknown [10.163.82.200]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 028383F70D; Sun, 22 Nov 2020 18:43:16 -0800 (PST) Subject: Re: [RFC 00/11] arm64: coresight: Enable ETE and TRBE To: Tingwei Zhang References: <1605012309-24812-1-git-send-email-anshuman.khandual@arm.com> <20201114051715.GA23685@codeaurora.org> From: Anshuman Khandual Message-ID: <8f323987-3327-1352-b097-8c018cc8d575@arm.com> Date: Mon, 23 Nov 2020 08:13:14 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201114051715.GA23685@codeaurora.org> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201122_214319_912690_EE0F81D2 X-CRM114-Status: GOOD ( 19.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: coresight@lists.linaro.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello Tingwei, On 11/14/20 10:47 AM, Tingwei Zhang wrote: > Hi Anshuman, > > On Tue, Nov 10, 2020 at 08:44:58PM +0800, Anshuman Khandual wrote: >> This series enables future IP trace features Embedded Trace Extension (ETE) >> and Trace Buffer Extension (TRBE). This series depends on the ETM system >> register instruction support series [0] and the v8.4 Self hosted tracing >> support series (Jonathan Zhou) [1]. The tree is available here [2] for >> quick access. >> >> ETE is the PE (CPU) trace unit for CPUs, implementing future architecture >> extensions. ETE overlaps with the ETMv4 architecture, with additions to >> support the newer architecture features and some restrictions on the >> supported features w.r.t ETMv4. The ETE support is added by extending the >> ETMv4 driver to recognise the ETE and handle the features as exposed by the >> TRCIDRx registers. ETE only supports system instructions access from the >> host CPU. The ETE could be integrated with a TRBE (see below), or with the >> legacy CoreSight trace bus (e.g, ETRs). Thus the ETE follows same firmware >> description as the ETMs and requires a node per instance. >> >> Trace Buffer Extensions (TRBE) implements a per CPU trace buffer, which is >> accessible via the system registers and can be combined with the ETE to >> provide a 1x1 configuration of source & sink. TRBE is being represented >> here as a CoreSight sink. Primary reason is that the ETE source could work >> with other traditional CoreSight sink devices. As TRBE captures the trace >> data which is produced by ETE, it cannot work alone. >> >> TRBE representation here have some distinct deviations from a traditional >> CoreSight sink device. Coresight path between ETE and TRBE are not built >> during boot looking at respective DT or ACPI entries. Instead TRBE gets >> checked on each available CPU, when found gets connected with respective >> ETE source device on the same CPU, after altering its outward connections. >> ETE TRBE path connection lasts only till the CPU is online. But ETE-TRBE >> coupling/decoupling method implemented here is not optimal and would be >> reworked later on. > Only perf mode is supported in TRBE in current path. Will you consider > support sysfs mode as well in following patch sets? Yes, either in subsequent versions or later on, after first getting the perf based functionality enabled. Nonetheless, sysfs is also on the todo list as mentioned in the cover letter. - Anshuman _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel