From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-18.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E51D5C433EF for ; Tue, 7 Sep 2021 09:06:16 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B4DF3610CB for ; Tue, 7 Sep 2021 09:06:16 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org B4DF3610CB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:Cc:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=yV32XOtYLPxj6Yz3/NOtciD8qjw8FwcSbWBr2auzY3k=; b=WynGdD9Tjdcw/qBN098sDlr5up FDobPMFMw5iUAN9DUn9+gzMSl4fWBwDAzuyvMnJ7vmcuYxGAP2z5tDzKdFsAb/kkEjVVA/7+jN02s MmliNz9/QAZLYosPAXvmtbUMwhUnQgId1VzbIxYWAPfEBZbvT4zR/mtkp58WZ2Yuy54clNsEmyVhV 4DpIc74D7foO+3hKzAqeMIjviqQRm7U55T7BBV5bWsLRlRp6s1oZFsT0hcuxMlX/kfoW+nIqPp5/W OD0MfjzeVQuvfNh+3PPeurDM9a9/zsqgd7nWCNg3Tdxmha4132yRUDF+IF4J5YIJI7/uOFS0GeIS0 o78fbEgQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mNX2B-00347S-En; Tue, 07 Sep 2021 09:04:51 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mNX23-00344c-24 for linux-arm-kernel@lists.infradead.org; Tue, 07 Sep 2021 09:04:45 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AF4BF31B; Tue, 7 Sep 2021 02:04:40 -0700 (PDT) Received: from [10.57.94.84] (unknown [10.57.94.84]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id DA1993F766; Tue, 7 Sep 2021 02:04:38 -0700 (PDT) Subject: Re: [PATCH 01/10] coresight: trbe: Add infrastructure for Errata handling To: Anshuman Khandual , linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, coresight@lists.linaro.org, will@kernel.org, catalin.marinas@arm.com, james.morse@arm.com, mathieu.poirier@linaro.org, mike.leach@linaro.org, leo.yan@linaro.org, maz@kernel.org, mark.rutland@arm.com References: <20210728135217.591173-1-suzuki.poulose@arm.com> <20210728135217.591173-2-suzuki.poulose@arm.com> <4c23e288-14bd-f4a5-2f92-6e3ad46324fa@arm.com> From: Suzuki K Poulose Message-ID: <919ef281-6ef2-8557-c8a3-e4eea452694f@arm.com> Date: Tue, 7 Sep 2021 10:04:37 +0100 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: <4c23e288-14bd-f4a5-2f92-6e3ad46324fa@arm.com> Content-Language: en-GB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210907_020443_260984_F32224B3 X-CRM114-Status: GOOD ( 36.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 02/08/2021 07:43, Anshuman Khandual wrote: > > > On 7/28/21 7:22 PM, Suzuki K Poulose wrote: >> Add a minimal infrastructure to keep track of the errata >> affecting the given TRBE instance. Given that we have >> heterogeneous CPUs, we have to manage the list per-TRBE >> instance to be able to apply the work around as needed. >> >> We rely on the arm64 errata framework for the actual >> description and the discovery of a given erratum, to >> keep the Erratum work around at a central place and >> benefit from the code and the advertisement from the >> kernel. We use a local mapping of the erratum to >> avoid bloating up the individual TRBE structures. > > I guess there is no other way around apart from each TRBE instance > tracking applicable erratas locally per CPU, even though it sounds > bit redundant. > >> i.e, each arm64 TRBE erratum bit is assigned a new number >> within the driver to track. Each trbe instance updates >> the list of affected erratum at probe time on the CPU. >> This makes sure that we can easily access the list of >> errata on a given TRBE instance without much overhead. > > It also ensures that the generic errata framework is queried just > once during individual CPU probe. > >> >> Cc: Mathieu Poirier >> Cc: Mike Leach >> Cc: Leo Yan >> Cc: Anshuman Khandual >> Signed-off-by: Suzuki K Poulose >> --- >> drivers/hwtracing/coresight/coresight-trbe.c | 48 ++++++++++++++++++++ >> 1 file changed, 48 insertions(+) >> >> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c >> index b8586c170889..0368bf405e35 100644 >> --- a/drivers/hwtracing/coresight/coresight-trbe.c >> +++ b/drivers/hwtracing/coresight/coresight-trbe.c >> @@ -16,6 +16,8 @@ >> #define pr_fmt(fmt) DRVNAME ": " fmt >> >> #include >> +#include >> + >> #include "coresight-self-hosted-trace.h" >> #include "coresight-trbe.h" >> >> @@ -65,6 +67,35 @@ struct trbe_buf { >> struct trbe_cpudata *cpudata; >> }; >> >> +/* >> + * TRBE erratum list >> + * >> + * We rely on the corresponding cpucaps to be defined for a given >> + * TRBE erratum. We map the given cpucap into a TRBE internal number >> + * to make the tracking of the errata lean. >> + * >> + * This helps in : >> + * - Not duplicating the detection logic >> + * - Streamlined detection of erratum across the system >> + * >> + * Since the erratum work arounds could be applied individually >> + * per TRBE instance, we keep track of the list of errata that >> + * affects the given instance of the TRBE. >> + */ >> +#define TRBE_ERRATA_MAX 0 >> + >> +static unsigned long trbe_errata_cpucaps[TRBE_ERRATA_MAX] = { >> +}; > > This needs to be tighten up. There should be build time guard rails in > arm64 errata cpucaps, so that only TRBE specific ones could be assigned > here as trbe_errata_cpucaps[]. I don't get your point. The actual arm64 erratum caps are not linear and as such we don't have to force it. This approach gives us a hand picked exact list of errata that apply to the TRBE driver by mapping it linearly here. The only reason why we have that TRBE_ERRATA_MAX, is such that we can track it per TRBE instance and ... > >> + >> +/* >> + * struct trbe_cpudata: TRBE instance specific data >> + * @trbe_flag - TRBE dirty/access flag support >> + * @tbre_align - Actual TRBE alignment required for TRBPTR_EL1. >> + * @cpu - CPU this TRBE belongs to. >> + * @mode - Mode of current operation. (perf/disabled) >> + * @drvdata - TRBE specific drvdata >> + * @errata - Bit map for the errata on this TRBE. >> + */ >> struct trbe_cpudata { >> bool trbe_flag; >> u64 trbe_align; >> @@ -72,6 +103,7 @@ struct trbe_cpudata { >> enum cs_mode mode; >> struct trbe_buf *buf; >> struct trbe_drvdata *drvdata; >> + DECLARE_BITMAP(errata, TRBE_ERRATA_MAX); >> }; >> >> struct trbe_drvdata { >> @@ -84,6 +116,21 @@ struct trbe_drvdata { >> struct platform_device *pdev; >> }; >> >> +static void trbe_check_errata(struct trbe_cpudata *cpudata) >> +{ >> + int i; >> + >> + for (i = 0; i < ARRAY_SIZE(trbe_errata_cpucaps); i++) { > > BUILD_BUG_ON() - if trbe_errata_cpucaps[i] is not inside TRBE specific > errata cpucap range ? ... also run these detection tests. > >> + if (this_cpu_has_cap(trbe_errata_cpucaps[i])) >> + set_bit(i, cpudata->errata); >> + } >> +} >> + >> +static inline bool trbe_has_erratum(int i, struct trbe_cpudata *cpudata) > > Switch the argument positions here ? 'int i' should be the second one. > ok. >> +{ >> + return (i < TRBE_ERRATA_MAX) && test_bit(i, cpudata->errata); >> +} >> + >> static int trbe_alloc_node(struct perf_event *event) >> { >> if (event->cpu == -1) >> @@ -925,6 +972,7 @@ static void arm_trbe_probe_cpu(void *info) >> goto cpu_clear; >> } >> >> + trbe_check_errata(cpudata); > > This should be called right at the end before arm_trbe_probe_cpu() exits > on the success path. Errata should not be evaluated if TRBE on the CPU > wont be used for some reason i.e cpumask_clear_cpu() path. ok > >> cpudata->trbe_align = 1ULL << get_trbe_address_align(trbidr); >> if (cpudata->trbe_align > SZ_2K) { >> pr_err("Unsupported alignment on cpu %d\n", cpu); >> > > This patch should be moved after [PATCH 5/10] i.e just before adding the > first TRBE errata. > I will take a look. Thanks for the review Suzuki _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel