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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oW1qo-009hF0-TF; Wed, 07 Sep 2022 20:40:47 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oW1ql-009hCj-R6 for linux-arm-kernel@lists.infradead.org; Wed, 07 Sep 2022 20:40:45 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F3EEF106F; Wed, 7 Sep 2022 13:40:46 -0700 (PDT) Received: from [10.57.15.197] (unknown [10.57.15.197]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 5CF203F7B4; Wed, 7 Sep 2022 13:40:28 -0700 (PDT) Message-ID: <9e537066-525f-4a8c-ffc1-926ac130c6e6@arm.com> Date: Wed, 7 Sep 2022 21:40:21 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:102.0) Gecko/20100101 Thunderbird/102.2.1 Subject: Re: [RFC PATCH v3 3/7] iommu/arm-smmu-v3: support ops registration for CDX bus Content-Language: en-GB To: Saravana Kannan Cc: "Gupta, Nipun" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "gregkh@linuxfoundation.org" , "rafael@kernel.org" , "eric.auger@redhat.com" , "alex.williamson@redhat.com" , "cohuck@redhat.com" , "Gupta, Puneet (DCG-ENG)" , "song.bao.hua@hisilicon.com" , "mchehab+huawei@kernel.org" , "maz@kernel.org" , "f.fainelli@gmail.com" , "jeffrey.l.hugo@gmail.com" , "Michael.Srba@seznam.cz" , "mani@kernel.org" , "yishaih@nvidia.com" , "jgg@ziepe.ca" , "jgg@nvidia.com" , "will@kernel.org" , "joro@8bytes.org" , "masahiroy@kernel.org" , "ndesaulniers@google.com" , "linux-arm-kernel@lists.infradead.org" , "linux-kbuild@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "kvm@vger.kernel.org" , "okaya@kernel.org" , "Anand, Harpreet" , "Agarwal, Nikhil" , "Simek, Michal" , "Radovanovic, Aleksandar" , "git (AMD-Xilinx)" References: <20220803122655.100254-1-nipun.gupta@amd.com> <20220906134801.4079497-1-nipun.gupta@amd.com> <20220906134801.4079497-4-nipun.gupta@amd.com> From: Robin Murphy In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220907_134044_015661_DDD63805 X-CRM114-Status: GOOD ( 22.09 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2022-09-07 19:24, Saravana Kannan wrote: > On Wed, Sep 7, 2022 at 1:27 AM Robin Murphy wrote: >> >> On 2022-09-07 04:17, Gupta, Nipun wrote: >>> [AMD Official Use Only - General] >>> >>> >>> >>>> -----Original Message----- >>>> From: Saravana Kannan >>>> Sent: Wednesday, September 7, 2022 5:41 AM >>>> To: Gupta, Nipun >>>> Cc: robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; >>>> gregkh@linuxfoundation.org; rafael@kernel.org; eric.auger@redhat.com; >>>> alex.williamson@redhat.com; cohuck@redhat.com; Gupta, Puneet (DCG-ENG) >>>> ; song.bao.hua@hisilicon.com; >>>> mchehab+huawei@kernel.org; maz@kernel.org; f.fainelli@gmail.com; >>>> jeffrey.l.hugo@gmail.com; Michael.Srba@seznam.cz; mani@kernel.org; >>>> yishaih@nvidia.com; jgg@ziepe.ca; jgg@nvidia.com; robin.murphy@arm.com; >>>> will@kernel.org; joro@8bytes.org; masahiroy@kernel.org; >>>> ndesaulniers@google.com; linux-arm-kernel@lists.infradead.org; linux- >>>> kbuild@vger.kernel.org; linux-kernel@vger.kernel.org; >>>> devicetree@vger.kernel.org; kvm@vger.kernel.org; okaya@kernel.org; Anand, >>>> Harpreet ; Agarwal, Nikhil >>>> ; Simek, Michal ; >>>> Radovanovic, Aleksandar ; git (AMD-Xilinx) >>>> >>>> Subject: Re: [RFC PATCH v3 3/7] iommu/arm-smmu-v3: support ops registration >>>> for CDX bus >>>> >>>> [CAUTION: External Email] >>>> >>>> On Tue, Sep 6, 2022 at 6:48 AM Nipun Gupta wrote: >>>>> >>>>> With new CDX bus supported for AMD FPGA devices on ARM >>>>> platform, the bus requires registration for the SMMU v3 >>>>> driver. >>>>> >>>>> Signed-off-by: Nipun Gupta >>>>> --- >>>>> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 16 ++++++++++++++-- >>>>> 1 file changed, 14 insertions(+), 2 deletions(-) >>>>> >>>>> diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c >>>> b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c >>>>> index d32b02336411..8ec9f2baf12d 100644 >>>>> --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c >>>>> +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c >>>>> @@ -29,6 +29,7 @@ >>>>> #include >>>>> >>>>> #include >>>>> +#include >>>>> >>>>> #include "arm-smmu-v3.h" >>>>> #include "../../iommu-sva-lib.h" >>>>> @@ -3690,16 +3691,27 @@ static int arm_smmu_set_bus_ops(struct >>>> iommu_ops *ops) >>>>> if (err) >>>>> goto err_reset_pci_ops; >>>>> } >>>>> +#endif >>>>> +#ifdef CONFIG_CDX_BUS >>>>> + if (cdx_bus_type.iommu_ops != ops) { >>>>> + err = bus_set_iommu(&cdx_bus_type, ops); >>>>> + if (err) >>>>> + goto err_reset_amba_ops; >>>>> + } >>>> >>>> I'm not an expert on IOMMUs, so apologies if the question is stupid. >>>> >>>> Why does the CDX bus need special treatment here (like PCI) when there >>>> are so many other busses (eg: I2C, SPI, etc) that don't need any >>>> changes here? >>> >>> AFAIU, the devices on I2C/SPI does not use SMMU. Apart from PCI/AMBA, >>> FSL-MC is another similar bus (on SMMUv2) which uses SMMU ops. >>> >>> The devices here are behind SMMU. Robin can kindly correct or add >>> more here from SMMU perspective. >> >> Indeed, there is no need to describe and handle how DMA may or may not >> be translated for I2C/SPI/USB/etc. because they are not DMA-capable >> buses (in those cases the relevant bus *controller* often does DMA, but >> it does that for itself as the platform/PCI/etc. device it is). > > Ok this is what I was guessing was the reason, but didn't want to make > that assumption. > > So if there are other cases like AMBA, FSL-MC where the devices can do > direct DMA, why do those buses not need a #ifdef section in this > function like CDX? Or put another way, why does CDX need special treatment? Er, it doesn't? The only non-optional bus here is platform, since the others *can* be configured out and *are* #ifdefed accordingly. This patch is fine for the kernel it was based on, it'll just want rewriting now that I've cleaned all this horrible driver boilerplate up. And according to the thread on patch #4 there might need to be additional changes for CDX to express a reserved MSI region for SMMU support to actually work properly. Robin. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel