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From: Peng Fan <peng.fan@nxp.com>
To: Stephen Boyd <sboyd@kernel.org>,
	"mturquette@baylibre.com" <mturquette@baylibre.com>,
	"s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
	 "shawnguo@kernel.org" <shawnguo@kernel.org>
Cc: Jacky Bai <ping.bai@nxp.com>, Anson Huang <anson.huang@nxp.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	dl-linux-imx <linux-imx@nxp.com>,
	"kernel@pengutronix.de" <kernel@pengutronix.de>,
	"festevam@gmail.com" <festevam@gmail.com>,
	"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	Abel Vesa <abel.vesa@nxp.com>
Subject: RE: [PATCH] clk: imx8mn: fix int pll clk gate
Date: Mon, 19 Aug 2019 01:05:42 +0000
Message-ID: <AM0PR04MB4481D73817CFCB7491DE89CB88A80@AM0PR04MB4481.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <20190816180246.D37BD20665@mail.kernel.org>

Hi Stephen,

> Subject: Re: [PATCH] clk: imx8mn: fix int pll clk gate
> 
> Quoting peng.fan@nxp.com (2019-08-13 18:53:12)
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > To Frac pll, the gate shift is 13, however to Int PLL the gate shift
> > is 11.
> >
> > Cc: <stable@vger.kernel.org>
> > Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver")
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > Reviewed-by: Jacky Bai <ping.bai@nxp.com>
> > ---
> 
> This is a fix for a change in -next. Why is stable Cced?

Sorry, that was added by mistaken. Should I resend v2 to drop it?

Thanks,
Peng.

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Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-14  1:53 peng.fan
2019-08-16 18:02 ` Stephen Boyd
2019-08-19  1:05   ` Peng Fan [this message]
2019-08-19 11:59     ` Shawn Guo

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