From: Ran Wang <ran.wang_1@nxp.com>
To: Rob Herring <robh@kernel.org>
Cc: "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
Biwen Li <biwen.li@nxp.com>, Shawn Guo <shawnguo@kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Leo Li <leoyang.li@nxp.com>,
"linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: RE: [PATCH 1/5] Documentation: dt: binding: fsl: Add 'fsl,ippdexpcr1-alt-addr' property
Date: Sun, 27 Sep 2020 07:23:33 +0000 [thread overview]
Message-ID: <AM6PR04MB5413C58E6BB5FB08DF980564F1340@AM6PR04MB5413.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <AM6PR04MB5413BB2F8D044B2312DAEC4FF1380@AM6PR04MB5413.eurprd04.prod.outlook.com>
Hi Rob
Not sure whether you have missed this mail with my query.
Regards,
Ran
On Wednesday, September 23, 2020 2:44 PM Ran Wang wrote:
>
> Hi Rob,
>
> On Wednesday, September 23, 2020 10:33 AM, Rob Herring wrote:
> >
> > On Wed, Sep 16, 2020 at 04:18:27PM +0800, Ran Wang wrote:
> > > From: Biwen Li <biwen.li@nxp.com>
> > >
> > > The 'fsl,ippdexpcr1-alt-addr' property is used to handle an errata
> > > A-008646 on LS1021A
> > >
> > > Signed-off-by: Biwen Li <biwen.li@nxp.com>
> > > Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
> > > ---
> > > Documentation/devicetree/bindings/soc/fsl/rcpm.txt | 19
> > > +++++++++++++++++++
> > > 1 file changed, 19 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > > b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > > index 5a33619..1be58a3 100644
> > > --- a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > > +++ b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > > @@ -34,6 +34,11 @@ Chassis Version Example Chips
> > > Optional properties:
> > > - little-endian : RCPM register block is Little Endian. Without it RCPM
> > > will be Big Endian (default case).
> > > + - fsl,ippdexpcr1-alt-addr : The property is related to a hardware issue
> > > + on SoC LS1021A and only needed on SoC LS1021A.
> > > + Must include 2 entries:
> > > + The first entry must be a link to the SCFG device node.
> > > + The 2nd entry must be offset of register IPPDEXPCR1 in SCFG.
> >
> > You don't need a DT change for this. You can find SCFG node by its
> > compatible string and then the offset should be known given this issue is
> only on 1 SoC.
>
> Did you mean that RCPM driver just to access IPPDEXPCR1 shadowed register
> in SCFG directly without fetching it's offset info. from DT?
>
> Regards,
> Ran
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next prev parent reply other threads:[~2020-09-27 7:25 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-16 8:18 [PATCH 1/5] Documentation: dt: binding: fsl: Add 'fsl, ippdexpcr1-alt-addr' property Ran Wang
2020-09-16 8:18 ` [PATCH 2/5] soc: fsl: handle RCPM errata A-008646 on SoC LS1021A Ran Wang
2020-09-21 22:42 ` Leo Li
2020-09-22 2:16 ` Ran Wang
2020-09-16 8:18 ` [PATCH 3/5] arm: dts: ls1021a: fix that FlexTimer cannot wakeup system in deep sleep Ran Wang
2020-09-21 22:58 ` Leo Li
2020-09-22 2:18 ` Ran Wang
2020-09-16 8:18 ` [PATCH 4/5] arm: dts: ls1021a: fix flextimer failed to wake system Ran Wang
2020-09-21 23:01 ` Leo Li
2020-09-16 8:18 ` [PATCH 5/5] arm: dts: ls1021a: fix rcpm failed to claim resource Ran Wang
2020-09-21 21:57 ` Leo Li
2020-09-21 22:20 ` [PATCH 1/5] Documentation: dt: binding: fsl: Add 'fsl,ippdexpcr1-alt-addr' property Leo Li
2020-09-22 2:12 ` Ran Wang
2020-09-23 2:32 ` Rob Herring
2020-09-23 6:44 ` Ran Wang
2020-09-27 7:23 ` Ran Wang [this message]
2020-09-28 13:56 ` Rob Herring
2020-09-29 0:34 ` Ran Wang
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