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Wed, 12 May 2021 01:58:17 -0700 (PDT) MIME-Version: 1.0 References: <20210511144252.3779113-1-tabba@google.com> <20210511144252.3779113-2-tabba@google.com> <22ccf11e-89ac-75f6-0adc-c1130811c5e5@arm.com> In-Reply-To: <22ccf11e-89ac-75f6-0adc-c1130811c5e5@arm.com> From: Fuad Tabba Date: Wed, 12 May 2021 09:57:40 +0100 Message-ID: Subject: Re: [PATCH v1 01/13] arm64: Do not enable uaccess for flush_icache_range To: Robin Murphy Cc: "moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)" , Will Deacon , Catalin Marinas , Mark Rutland , Marc Zyngier , ardb@kernel.org, James Morse , Alexandru Elisei , Suzuki K Poulose X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210512_015818_612955_93D19672 X-CRM114-Status: GOOD ( 15.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Robin, > > -SYM_FUNC_START(__flush_cache_user_range) > > +.macro __flush_cache_range, needs_uaccess > > + .if \needs_uaccess > > uaccess_ttbr0_enable x2, x3, x4 > > + .endif > > Nit: this feels like it belongs directly in __flush_cache_user_range() > rather than being hidden in the macro, since it's not really an integral > part of the cache maintenance operation itself. I will fix this in v2. Thanks, /fuad > Robin. > > > alternative_if ARM64_HAS_CACHE_IDC > > dsb ishst > > b 7f > > @@ -47,7 +37,11 @@ alternative_else_nop_endif > > sub x3, x2, #1 > > bic x4, x0, x3 > > 1: > > + .if \needs_uaccess > > user_alt 9f, "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE > > + .else > > +alternative_insn "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE > > + .endif > > add x4, x4, x2 > > cmp x4, x1 > > b.lo 1b > > @@ -58,15 +52,47 @@ alternative_if ARM64_HAS_CACHE_DIC > > isb > > b 8f > > alternative_else_nop_endif > > - invalidate_icache_by_line x0, x1, x2, x3, 9f > > + invalidate_icache_by_line x0, x1, x2, x3, \needs_uaccess, 9f > > 8: mov x0, #0 > > 1: > > + .if \needs_uaccess > > uaccess_ttbr0_disable x1, x2 > > + .endif > > ret > > + > > + .if \needs_uaccess > > 9: > > mov x0, #-EFAULT > > b 1b > > + .endif > > +.endm > > + > > +/* > > + * flush_icache_range(start,end) > > + * > > + * Ensure that the I and D caches are coherent within specified region. > > + * This is typically used when code has been written to a memory region, > > + * and will be executed. > > + * > > + * - start - virtual start address of region > > + * - end - virtual end address of region > > + */ > > +SYM_FUNC_START(__flush_icache_range) > > + __flush_cache_range needs_uaccess=0 > > SYM_FUNC_END(__flush_icache_range) > > + > > +/* > > + * __flush_cache_user_range(start,end) > > + * > > + * Ensure that the I and D caches are coherent within specified region. > > + * This is typically used when code has been written to a memory region, > > + * and will be executed. > > + * > > + * - start - virtual start address of region > > + * - end - virtual end address of region > > + */ > > +SYM_FUNC_START(__flush_cache_user_range) > > + __flush_cache_range needs_uaccess=1 > > SYM_FUNC_END(__flush_cache_user_range) > > > > /* > > @@ -86,7 +112,7 @@ alternative_else_nop_endif > > > > uaccess_ttbr0_enable x2, x3, x4 > > > > - invalidate_icache_by_line x0, x1, x2, x3, 2f > > + invalidate_icache_by_line x0, x1, x2, x3, 1, 2f > > mov x0, xzr > > 1: > > uaccess_ttbr0_disable x1, x2 > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel