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bh=FWtdDuSKaLUXcujU5F4tqzi/gqM6kON5tve8kEsdyNo=; b=j1UE8f8TGMLXTBfqib/qp/d1bkYQf6YVgHUvXDO6uNNnI1/p0YoLyfU4SigNUPmvI/ LKTEaxI9ssnCygnbpnpYOiFsIhsi1t5szR980BBKjmb5K0F/Ot0YabE3FBieT/62voS8 qWpgzsL8TnEg95rblmKgx8oGZ3tz5zN8uaQKAidtYXmATJjUeBxvgflQ9uiGcom6Jory g7YNj5JJZsuYx0VK0M9msn8JcmvC07Y4VrEPrB57AeTQSFtIFHHSZkHQC9EXlqOkk7fK HPAwOJTmBhB/62lpiXIq3dAAIbHXogkf2UQgijNcmYUCDUk440Lc1DRRwCDjJ0vUY0NL r2qg== X-Gm-Message-State: AOAM530dWUJ6Z9dJmymMNgT2S0URYZXMM6M1AHejpblHCdMshy/uriQP eSOa8dkc0pNO0gxN2dxj0XA+tiWahksWAqhlC14= X-Google-Smtp-Source: ABdhPJw7Ho+BnwKzS9opX/ah1rN3NfhTEL7mMbkREE72S2PvJVZGoSa1QSqPlIv08eHOhsje4FZ4s7m5L9h8qEttD3A= X-Received: by 2002:a25:208:: with SMTP id 8mr15530089ybc.47.1621622581067; Fri, 21 May 2021 11:43:01 -0700 (PDT) MIME-Version: 1.0 References: <20210514192218.13022-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20210514192218.13022-12-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: "Lad, Prabhakar" Date: Fri, 21 May 2021 19:42:35 +0100 Message-ID: Subject: Re: [PATCH 11/16] dt-bindings: clock: renesas: Document RZ/G2L SoC CPG driver To: Geert Uytterhoeven Cc: Lad Prabhakar , Rob Herring , Magnus Damm , Michael Turquette , Stephen Boyd , Greg Kroah-Hartman , Catalin Marinas , Will Deacon , Jiri Slaby , Philipp Zabel , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux Kernel Mailing List , Linux-Renesas , linux-clk , "open list:SERIAL DRIVERS" , Linux ARM , Biju Das X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210521_114302_078159_EE752D60 X-CRM114-Status: GOOD ( 32.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Geert, Thank you for the review. On Fri, May 21, 2021 at 4:04 PM Geert Uytterhoeven wrote: > > Hi Prabhakar, > > On Fri, May 14, 2021 at 9:23 PM Lad Prabhakar > wrote: > > Document the device tree bindings of the Renesas RZ/G2L SoC clock > > driver in Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml. > > > > Signed-off-by: Lad Prabhakar > > Reviewed-by: Biju Das > > Thanks for your patch! > > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml > > @@ -0,0 +1,80 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#" > > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > > + > > +title: Renesas RZ/G2L Clock Pulse Generator / Module Stop and Software Reset > > (Module Standby Mode > > + > > +maintainers: > > + - Geert Uytterhoeven > > + > > +description: | > > + On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and MSTP > > + (Module Stop and Software Reset) share the same register block. > > + > > + They provide the following functionalities: > > + - The CPG block generates various core clocks, > > + - The MSTP block provides two functions: > > + 1. Module Stop, providing a Clock Domain to control the clock supply > > + to individual SoC devices, > > + 2. Reset Control, to perform a software reset of individual SoC devices. > > + > > +properties: > > + compatible: > > + const: renesas,r9a07g044l-cpg # RZ/G2L > > renesas,r9a07g044-cpg? > As some IP blocks present in RZ/G2L aren't present in RZ/G2LC clock handling will differ so as a result SoC specific compatible string is added. > I believe it's the same block on RZ/G2L ('044l) and RZ/G2LC ('044c). > > > + '#clock-cells': > > + description: | > > + - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" > > + and a core clock reference, as defined in > > + > > > Indeed > > + - For module clocks, the two clock specifier cells must be "CPG_MOD" and > > + a module number, as defined in the datasheet. > > Also in ? > Agreed. > > + const: 2 > > + > > + '#power-domain-cells': > > + description: > > + SoC devices that are part of the CPG/MSTP Clock Domain and can be > > + power-managed through Module Stop should refer to the CPG device node > > + in their "power-domains" property, as documented by the generic PM Domain > > + bindings in Documentation/devicetree/bindings/power/power-domain.yaml. > > + const: 0 > > + > > + '#reset-cells': > > + description: > > + The single reset specifier cell must be the module number, as defined in > > + the datasheet. > > Also in ? > Agreed. Cheers, Prabhakar > > + const: 1 > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel