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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=6+VUqgiuTjQeU7l/kUlUaXroa9OGkZIBVKyyM//tCkE=; b=qtn1CBwYzjEmML2MC/0MUvsvVvphZiSiBZiAMlgK+nI9jQTOF9urBx0L8qDuZsxIG1 JWt1RbWvaIOLk5R/uz8ahBXd78XKNvbmgrlm39ATnzyPTaI/AcJ0S4kqS66fE2uNR94j LFUbMZCmaTJ7crFH0Z53N6NIPG0KeIujP7GiUykNg6ghHiXhL9DPbBQL1NzWm9ThPCEr s5gXt4xIZo2wC0BT+roVWMFvmklmIJ1TtN+AOiVZxoGpPqI6I9duomY3VjkZ24MvygDF fefXkZQcHKBhpbL/xGYgUAP63eftdhCsE+hpUF/ZelYrKVcNPZX9HBQpc398EtxryTUC F0Ng== X-Gm-Message-State: ACrzQf1jU02Tuq6N7rYTpYiJB0/5/sHiee1QJDrpjOax0P0oT99jTBvY b9vR6KfQpFNX99Di03/SlzSfRrrIPMuEXiS3Yu8= X-Google-Smtp-Source: AMsMyM5uf3VBi7wDQS52pr75/TL9qL/dFM8EyIsrXPwepN7iHNubY9D8z0yViEy8YHNOHkmbJ1lJGMTwWDU1EbB6m/Q= X-Received: by 2002:a05:6402:40c6:b0:459:6749:9e1f with SMTP id z6-20020a05640240c600b0045967499e1fmr17085133edb.319.1665394921761; Mon, 10 Oct 2022 02:42:01 -0700 (PDT) MIME-Version: 1.0 References: <20220929172356.301342-1-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20220929172356.301342-1-prabhakar.mahadev-lad.rj@bp.renesas.com> From: "Lad, Prabhakar" Date: Mon, 10 Oct 2022 10:41:35 +0100 Message-ID: Subject: Re: [RFC PATCH 0/2] RZ/G2UL separate out SoC specific parts To: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski Cc: Conor Dooley , Samuel Holland , linux-riscv , Linux ARM , Linux-Renesas , DT , LKML , Biju Das , Lad Prabhakar X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221010_024207_114920_E2A3E177 X-CRM114-Status: GOOD ( 19.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Rob, Krzysztof, On Thu, Sep 29, 2022 at 6:24 PM Prabhakar wrote: > > From: Lad Prabhakar > > Hi All, > > This patch series aims to split up the RZ/G2UL SoC DTSI into common parts > so that this can be shared with the RZ/Five SoC. > > Implementation is based on the discussion [0] where I have used option#2. > > The Renesas RZ/G2UL (ARM64) and RZ/Five (RISC-V) have almost the same > identical blocks to avoid duplication a base SoC dtsi (r9a07g043.dtsi) is > created which will be used by the RZ/G2UL (r9a07g043u.dtsi) and RZ/Five > (r9a07g043F.dtsi) > > Sending this as an RFC to get some feedback. > > r9a07g043f.dtsi will look something like below: > > #include > > #define SOC_PERIPHERAL_IRQ_NUMBER(nr) (nr + 32) > #define SOC_PERIPHERAL_IRQ(nr, na) SOC_PERIPHERAL_IRQ_NUMBER(nr) na > > #include > > / { > ... > ... > }; > > Although patch#2 can be merged into patch#1 just wanted to keep them separated > for easier review. > > [0] https://lore.kernel.org/linux-arm-kernel/Yyt8s5+pyoysVNeC@spud/T/ > > Cheers, > Prabhakar > > Lad Prabhakar (2): > arm64: dts: renesas: r9a07g043: Introduce SOC_PERIPHERAL_IRQ() macro > to specify interrupt property Can either of you please review patch #1. Cheers, Prabhakar > arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts > > arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 362 +++++++----------- > arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 87 +++++ > .../boot/dts/renesas/r9a07g043u11-smarc.dts | 2 +- > 3 files changed, 235 insertions(+), 216 deletions(-) > create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u.dtsi > > -- > 2.25.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel