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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=7B3KT7m27I86KEF7GR0Y9+xEe3Sei4avLWRZmXEU+Jk=; b=XIaz1e6xHJjxIn7VFx6hAW7ZqVKHDD/qy8AKcRWB0DGCRwm9sSa6X5EIMQg2CtT2Mr F7lu2wrVjPVsF8nYyONpbi9nPa8htIg15/8FOnDXJyZBCC7k/kq080AXJU+6Ck3ecBQ5 5hE3d/fnPkShgWRyOw33D5bdXg4AsfxsWXXJZhhDPIDpxGxvUClhubeLeH8hUzjPgLjT kYVm0LeZJXiX3Y1kqArrirtcDJkVu43DyhDa3o16sV0b2VmQPsD9jEmHiJdU3HFq3cr3 ncod7pZV9jyCgrdBM7bOaivYZyHTV1MIuPScWVzsOnNrUqvifW+pnYPIIJUzPx6J8XkG HODg== X-Gm-Message-State: APjAAAXp6ojNIc35u44s8FbRU+DVyl9Hkmw4c/GwyhmnUmjLFZApRnH/ kN0qfus8lsIjZRdk4cGYh6pr13wm0Zx6mB/I3Cg= X-Google-Smtp-Source: APXvYqw2xy+TORlK9D3NsUd6J7Zs/SmAvifrskcUq5ND66YP9APND+9oBSZCimLdnMzy1MQF2p48oh0a34pC8u3dbWo= X-Received: by 2002:a50:b63b:: with SMTP id b56mr16737146ede.165.1573312912091; Sat, 09 Nov 2019 07:21:52 -0800 (PST) MIME-Version: 1.0 Received: by 2002:a17:906:12cf:0:0:0:0 with HTTP; Sat, 9 Nov 2019 07:21:51 -0800 (PST) In-Reply-To: <20191109150953.GJ22978@lunn.ch> References: <20191109105642.30700-1-olteanv@gmail.com> <20191109150953.GJ22978@lunn.ch> From: Vladimir Oltean Date: Sat, 9 Nov 2019 17:21:51 +0200 Message-ID: Subject: Re: [PATCH] ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs To: Andrew Lunn X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191109_072155_497874_62926328 X-CRM114-Status: GOOD ( 11.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, leoyang.li@nxp.com, robh+dt@kernel.org, shawnguo@kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 09/11/2019, Andrew Lunn wrote: > On Sat, Nov 09, 2019 at 12:56:42PM +0200, Vladimir Oltean wrote: >> On the LS1021A-TSN board, the 2 Atheros AR8031 PHYs for eth0 and eth1 >> have interrupt lines connected to the shared IRQ2_B LS1021A pin. >> >> The interrupts are active low, but the GICv2 controller does not support >> active-low and falling-edge interrupts, so the only mode it can be >> configured in is rising-edge. > > Hi Vladimir > > So how does this work? The rising edge would occur after the interrupt > handler has completed? What triggers the interrupt handler? > > Andrew > Hi Andrew, I hope I am not terribly confused about this. I thought I am telling the interrupt controller to raise an IRQ as a result of the low-to-high transition of the electrical signal. Experimentation sure seems to agree with me. So the IRQ is generated immediately _after_ the PHY has left the line in open drain and it got pulled up to Vdd. Thanks, -Vladimir [Sorry for the repost, for some reason Gmail decided to send this email as html earlier] _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel