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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=8zojunifusLfr1jEnEqSjmYR20WZ1fEsNzo7A4tHyP4=; b=P7UFn5czzXVcQZbv13FIlb2bc9Pf0nqqYvVfsvIzUkBgjMnCV7VwiOIsQtHeENC8pX jI+h1FGQsL0TKn+QRXe0DYV9NbcypI/DE9zFq9muWzL/oCP52r/Pf5HTSvURLwENo11s 1rMKaMyQ9wIMYqFurfmXszDR8yvX93zMrdnI6u9PwaJ+cSNtOhF0Kzx/36yrH/6sC5KO 67I6g3GT5vQAhcHO5XJfF81+Iq/W1YfD/zFrnM8GrtBY49wKD0zy36E88wbiPrVK17LN YZHMoQ5HdWnl4UnmR3hnzAlrYOMQF+jQOCm879x6bJjn+CryA3+QSdKJ5hNAJ3Vg6kPY Ga6A== X-Gm-Message-State: APjAAAWuXGPmlCjFh5NLvwszBdGIuEPPWCM0VmtdEd4JkVp3raA0QY7n mzliYKCtUqhGFa4mXzSireKdcIDV3fdQxfx4jGw= X-Google-Smtp-Source: APXvYqzN0POuwv56LXfez+H6xjZkYp5GeQpjPOMQc4iIa4vxocTm7F9V1LtTp49CZtcIduerqAiinNINZ7IzqarUkHk= X-Received: by 2002:a17:906:3450:: with SMTP id d16mr3032396ejb.216.1573336620802; Sat, 09 Nov 2019 13:57:00 -0800 (PST) MIME-Version: 1.0 References: <20191109105642.30700-1-olteanv@gmail.com> <20191109150953.GJ22978@lunn.ch> <393335751.FoSYQk3TTC@kongar> <20191109210549.GB12999@lunn.ch> In-Reply-To: From: Vladimir Oltean Date: Sat, 9 Nov 2019 23:56:49 +0200 Message-ID: Subject: Re: [PATCH] ARM: dts: ls1021a-tsn: Use interrupts for the SGMII PHYs To: Andrew Lunn , Alexander Stein , Kurt Kanzenbach , Rasmus Villemoes X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191109_135702_800026_5105CBA7 X-CRM114-Status: GOOD ( 24.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, netdev , lkml , leoyang.li@nxp.com, Rob Herring , Shawn Guo , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, 9 Nov 2019 at 23:37, Vladimir Oltean wrote: > > On Sat, 9 Nov 2019 at 23:05, Andrew Lunn wrote: > > > > On Sat, Nov 09, 2019 at 08:52:54PM +0100, Alexander Stein wrote: > > > On Saturday, November 9, 2019, 4:21:51 PM CET Vladimir Oltean wrote: > > > > On 09/11/2019, Andrew Lunn wrote: > > > > > On Sat, Nov 09, 2019 at 12:56:42PM +0200, Vladimir Oltean wrote: > > > > >> On the LS1021A-TSN board, the 2 Atheros AR8031 PHYs for eth0 and eth1 > > > > >> have interrupt lines connected to the shared IRQ2_B LS1021A pin. > > > > >> > > > > >> The interrupts are active low, but the GICv2 controller does not support > > > > >> active-low and falling-edge interrupts, so the only mode it can be > > > > >> configured in is rising-edge. > > > > > > > > > > Hi Vladimir > > > > > > > > > > So how does this work? The rising edge would occur after the interrupt > > > > > handler has completed? What triggers the interrupt handler? > > > > > > > > > > Andrew > > > > > > > > > > > > > Hi Andrew, > > > > > > > > I hope I am not terribly confused about this. I thought I am telling > > > > the interrupt controller to raise an IRQ as a result of the > > > > low-to-high transition of the electrical signal. Experimentation sure > > > > seems to agree with me. So the IRQ is generated immediately _after_ > > > > the PHY has left the line in open drain and it got pulled up to Vdd. > > > > > > > > It is correct GIC only supports raising edge and active-high. The > > > IRQ[0:5] on ls1021a are a bit special though. They not directly > > > connected to GIC, but there is an optional inverter, enabled by > > > default. > > > > Ah, O.K. So configuring for a rising edge is actually giving a falling > > edge. Which is why it works. > > > > Actually supporting this correctly is going a cause some pain. I > > wonder how many DT files currently say rising/active high, when in > > fact falling/active low is actually being used? And when the IRQ > > controller really does support active low and falling, things brake? > > > > Vladimir, since this is a shared interrupt, you really should use > > active low here. Maybe the first step is to get control of the > > inverter, and define a DT binding which is not going to break > > backwards compatibility. And then wire up this interrupt. > > > > Andrew > > Oh, ok, this is what you mean, thanks Alexander for the clarification. > This sure escalated quickly and is going to keep me busy for a while. > > -Vladimir Sorry, I'm still a bit in shock, since this hit me in the face from nowhere, so I hadn't followed the entire history when I sent the above email. It looks after all that Kurt and Rasmus have picked this up again and that the latest patch set is from 2 days ago, I'll take a look at that... https://lwn.net/Articles/804103/ Thanks, -Vladimir _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel