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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=tpzREOcIrukXANPEmvrI6Q05nccQGVBf08+JNfkt4Jw=; b=uL0XYpHUrDJZnruSGaEXdAjx8mdIYhwUMQzaN4CeuznhjV8ysooV4zjSpIuuuWCLmB hZAKZOYPKWMAAPbOak2OcRDoxi3q3vlj98N6tzUyPjuBr8wKFJ7+hxE1C+Qnl0WBk7DU 6e71EDga8jZa5HS5R0nt8ZRlxqBP9aHLCfd3b5t98rdMf9evcZyrxkNtjHd3AEuwItIL gMJgH+pdSqndAoXP8/9Eeb9BeX5A/1bZtvu+RitRlEJhdta45B0ok02dg15msI/5R+1X fWxsfFiSuSbubUUr6M/UDqMuju4u7gXeYwLKB69WZzQ94mvO15dY24uPzjucUGWdu5yf pwug== X-Gm-Message-State: AOAM533R9xYAYNBAB4oK0yRbrsn/cckQxHytINUoujeiCV7YaARh5hza vPj4ClkRvOGeFtJXNsD1Rg+Ubx8CSefq4hCGOMJfkw== X-Google-Smtp-Source: ABdhPJxuj6rYCJJdWgpgaTNs6Y6dBbQY8aITvclQRebjC3+PxK6h72/GRkpCuz/1FNoHMmojX+ZiKylGPmUJot58C80= X-Received: by 2002:a63:4c:: with SMTP id 73mr14624887pga.286.1598532216123; Thu, 27 Aug 2020 05:43:36 -0700 (PDT) MIME-Version: 1.0 References: <518da1e5169a4e343caa3c37feed5ad551b77a34.1597425745.git.andreyknvl@google.com> <20200827104033.GF29264@gaia> <9c53dfaa-119e-b12e-1a91-1f67f4aef503@arm.com> <20200827111344.GK29264@gaia> In-Reply-To: From: Andrey Konovalov Date: Thu, 27 Aug 2020 14:43:25 +0200 Message-ID: Subject: Re: [PATCH 26/35] kasan, arm64: Enable TBI EL1 To: Vincenzo Frascino X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200827_084339_823841_050AF5E3 X-CRM114-Status: GOOD ( 20.68 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Linux ARM , Marco Elver , Elena Petrova , Catalin Marinas , Kevin Brodsky , Will Deacon , Branislav Rankov , kasan-dev , LKML , Linux Memory Management List , Alexander Potapenko , Evgenii Stepanov , Andrey Ryabinin , Andrew Morton , Dmitry Vyukov Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Aug 27, 2020 at 1:15 PM Vincenzo Frascino wrote: > > > > On 8/27/20 12:13 PM, Catalin Marinas wrote: > > On Thu, Aug 27, 2020 at 12:05:55PM +0100, Vincenzo Frascino wrote: > >> On 8/27/20 11:40 AM, Catalin Marinas wrote: > >>> On Fri, Aug 14, 2020 at 07:27:08PM +0200, Andrey Konovalov wrote: > >>>> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S > >>>> index 152d74f2cc9c..6880ddaa5144 100644 > >>>> --- a/arch/arm64/mm/proc.S > >>>> +++ b/arch/arm64/mm/proc.S > >>>> @@ -38,7 +38,7 @@ > >>>> /* PTWs cacheable, inner/outer WBWA */ > >>>> #define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA > >>>> > >>>> -#ifdef CONFIG_KASAN_SW_TAGS > >>>> +#if defined(CONFIG_KASAN_SW_TAGS) || defined(CONFIG_KASAN_HW_TAGS) > >>>> #define TCR_KASAN_FLAGS TCR_TBI1 > >>>> #else > >>>> #define TCR_KASAN_FLAGS 0 > >>> > >>> I prefer to turn TBI1 on only if MTE is present. So on top of the v8 > >>> user series, just do this in __cpu_setup. > >> > >> Not sure I understand... Enabling TBI1 only if MTE is present would break > >> KASAN_SW_TAGS which is based on TBI1 but not on MTE. > > > > You keep the KASAN_SW_TAGS as above but for HW_TAGS, only set TBI1 later > > in __cpu_setup(). > > > > Ok, sounds good. Sounds good to me too. Vincenzo, could you take care of Catalin's comments on your (arm64) patches, do the rebase onto user mte v8, and share it with me? I'll work on KASAN changes in the meantime, and then integrate everything together for v2. Perhaps the best way to test only the arm64 part is writing a simple module that causes an MTE fault. (At least that's what I did when I was testing core in-kernel MTE patches separately.) Or reuse this series, all KASAN patches should rebase cleanly on top of the latest mainline. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel