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From: zhang.lyra@gmail.com (Chunyan Zhang)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH V6 01/12] drivers: move clock common macros out from vendor directories
Date: Thu, 7 Dec 2017 16:08:37 +0800	[thread overview]
Message-ID: <CAAfSe-ufFDXTxUxTSW8Au9wdwoHKcB6RBdVdX36RrZQC4x0knw@mail.gmail.com> (raw)
In-Reply-To: <20171207064723.GV4283@codeaurora.org>

On 7 December 2017 at 14:47, Stephen Boyd <sboyd@codeaurora.org> wrote:
> On 11/27, Chunyan Zhang wrote:
>> These macros are used by more than one SoC vendor platforms, avoid to
>> have many copies of these code, this patch moves them to the common
>> clock directory which every clock drivers can access to.
>>
>> Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
>> ---
>>  drivers/clk/clk_common.h | 60 ++++++++++++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 60 insertions(+)
>>  create mode 100644 drivers/clk/clk_common.h
>>
>> diff --git a/drivers/clk/clk_common.h b/drivers/clk/clk_common.h
>> new file mode 100644
>> index 0000000..21e93d2
>> --- /dev/null
>> +++ b/drivers/clk/clk_common.h
>> @@ -0,0 +1,60 @@
>> +/*
>> + * drivers/clk/clk_common.h
>
> We don't need this in the file too. Please remove this line.
>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0
>> + */
>> +
>> +#ifndef _CLK_COMMON_H_
>> +#define _CLK_COMMON_H_
>> +
>> +#include <linux/clk-provider.h>
>
> Maybe these macros should just go into clk-provider.h?

Ok.  And I will also remove the same macros from sunxi-ng/ccu_common.h
and zte/clk.h.

>
>> +
>> +#define CLK_HW_INIT(_name, _parent, _ops, _flags)            \
>> +     (&(struct clk_init_data) {                              \
>> +             .flags          = _flags,                       \
>> +             .name           = _name,                        \
>> +             .parent_names   = (const char *[]) { _parent }, \
>> +             .num_parents    = 1,                            \
>> +             .ops            = _ops,                         \
>> +     })
>
> Hopefully we don't extend the init structure anymore to have
> something else. I guess we'll do something if that happens.
>
>> +
>> +#define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags)   \
>> +     (&(struct clk_init_data) {                              \
>> +             .flags          = _flags,                       \
>> +             .name           = _name,                        \
>> +             .parent_names   = _parents,                     \
>> +             .num_parents    = ARRAY_SIZE(_parents),         \
>> +             .ops            = _ops,                         \
>> +     })
>> +
>> +#define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags)     \
>> +     (&(struct clk_init_data) {                      \
>> +             .flags          = _flags,               \
>> +             .name           = _name,                \
>> +             .parent_names   = NULL,                 \
>> +             .num_parents    = 0,                    \
>> +             .ops            = _ops,                 \
>> +     })
>> +
>> +#define CLK_FIXED_FACTOR(_struct, _name, _parent,                    \
>> +                     _div, _mult, _flags)                            \
>> +     struct clk_fixed_factor _struct = {                             \
>> +             .div            = _div,                                 \
>> +             .mult           = _mult,                                \
>> +             .hw.init        = CLK_HW_INIT(_name,                    \
>> +                                           _parent,                  \
>> +                                           &clk_fixed_factor_ops,    \
>> +                                           _flags),                  \
>> +     }
>> +
>> +#define CLK_FIXED_RATE(_struct, _name, _flags,                               \
>> +                    _fixed_rate, _fixed_accuracy)                    \
>> +     struct clk_fixed_rate _struct = {                               \
>> +             .fixed_rate     = _fixed_rate,                          \
>> +             .fixed_accuracy = _fixed_accuracy,                      \
>> +             .hw.init        = CLK_HW_INIT_NO_PARENT(_name,          \
>> +                                       &clk_fixed_rate_ops,          \
>> +                                                     _flags),        \
>> +     }
>
> Maybe don't add this one? Usually fixed rate clks come from DT.

Ok, will also move the fixed rate clks from our driver to DT.

Thanks,
Chunyan

>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project

  reply	other threads:[~2017-12-07  8:08 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-11-27 10:01 [PATCH V6 00/12] add clock driver for Spreadtrum platforms Chunyan Zhang
2017-11-27 10:01 ` [PATCH V6 01/12] drivers: move clock common macros out from vendor directories Chunyan Zhang
2017-12-07  6:47   ` Stephen Boyd
2017-12-07  8:08     ` Chunyan Zhang [this message]
2017-11-27 10:01 ` [PATCH V6 02/12] clk: sprd: Add common infrastructure Chunyan Zhang
2017-12-07  6:50   ` Stephen Boyd
2017-11-27 10:01 ` [PATCH V6 03/12] clk: sprd: add gate clock support Chunyan Zhang
2017-11-27 10:01 ` [PATCH V6 04/12] clk: sprd: add mux " Chunyan Zhang
2017-11-27 10:01 ` [PATCH V6 05/12] clk: sprd: add divider " Chunyan Zhang
2017-11-27 10:01 ` [PATCH V6 06/12] clk: sprd: add composite " Chunyan Zhang
2017-11-27 10:01 ` [PATCH V6 07/12] clk: sprd: add adjustable pll support Chunyan Zhang
2017-11-27 10:01 ` [PATCH V6 08/12] dt-bindings: Add Spreadtrum clock binding documentation Chunyan Zhang
2017-11-27 10:01 ` [PATCH V6 09/12] clk: sprd: Add dt-bindings include file for SC9860 Chunyan Zhang
2017-11-27 10:01 ` [PATCH V6 10/12] clk: sprd: add clocks support " Chunyan Zhang
2017-11-27 10:01 ` [PATCH V6 11/12] arm64: dts: add syscon for whale2 platform Chunyan Zhang
2017-11-27 10:01 ` [PATCH V6 12/12] arm64: dts: add clocks for SC9860 Chunyan Zhang

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