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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=wQZ85dJNsIyQtNjnJDTR2ihKmDYZl4o1wc+cD1p5Uys=; b=Fjd70KCg5N9DIMmy8D789DGIxL3foCoz4GgxW0wu+UdKmKOGDAB2iZbZcsWR9IF2XR bOtphy5OY993bNVfVffq40G5OuTJl7bWaaCuvLYSSlHWHLkR5y2sXKlFfUQOdVNxrHcC QQjr/sY9Vaxi3NLZGlOK2GCDMTvW2iM/f9P8GxvpJS10rUmbhsQipe0pSZJ8S53SlveE 1V4Jlk1qzm0y5YaF6aOToIapsm6h5vmDLVr8E0uYLdrITE2gulzJtC8x2FZbcgmbXrjy 6365yFQ77JTbVimuNyrojD/nuNqOv1JAeVm0zKp8q0Y9Fy0oL9z+RtAVJxlpnPLc2Nz2 JkCA== X-Gm-Message-State: AOAM533X1cuG50L/YNgD5I+lCB4ETdfMma7G7exvMqkzYJRNRf90g2VZ cDuS3yW9Puokykt4s5np28RsDNMT01QB+m6dDJXB8Q== X-Google-Smtp-Source: ABdhPJw1Hr+9bP5FQEtUOU0p0RHYUw+Mo6ABI9TPDkRcxw0lXEEjdHuU++zVBajvD6EFYP2r4SQStnlEK25XtpZ3UuI= X-Received: by 2002:ac2:42d8:: with SMTP id n24mr3660836lfl.502.1602236323336; Fri, 09 Oct 2020 02:38:43 -0700 (PDT) MIME-Version: 1.0 References: <20201006142532.2247515-1-lars.povlsen@microchip.com> <20201006142532.2247515-3-lars.povlsen@microchip.com> <87ft6px9wc.fsf@soft-dev15.microsemi.net> In-Reply-To: <87ft6px9wc.fsf@soft-dev15.microsemi.net> From: Linus Walleij Date: Fri, 9 Oct 2020 11:38:32 +0200 Message-ID: Subject: Re: [RESEND PATCH v3 2/3] pinctrl: pinctrl-mchp-sgpio: Add pinctrl driver for Microsemi Serial GPIO To: Lars Povlsen X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201009_053845_860303_DB0F4F86 X-CRM114-Status: GOOD ( 13.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Alexandre Belloni , "linux-kernel@vger.kernel.org" , Microchip Linux Driver Support , "open list:GPIO SUBSYSTEM" , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Lars, I'm overall mostly happy with the latest posting (not the one I respond to here) On Thu, Oct 8, 2020 at 12:57 PM Lars Povlsen wrote: > > On Tue, Oct 6, 2020 at 4:25 PM Lars Povlsen wrote: > >> + gc->of_xlate = microchip_sgpio_of_xlate; > >> + gc->of_gpio_n_cells = 3; > > > > So I'm sceptical to this. > > > > Why can't you just use the pin index in cell 0 directly > > and avoid cell 1? > > > > You scepticism has surfaced before :-). The (now) 2 indices relates to > how the hardware address signals. > > Each signal/pin is addressed by port, bit number and direction. We now > have the direction encoded in the bank/phandle. I'm sorry but I just don't get it, I suppose. To me it is pretty straight-forward that the cells indicate the pin and then the flags. I do understand you need the port at all, since this is implicit from the reg property of the DT node. Are these two different things? Yours, Linus Walleij _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel