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s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=Sy4nEQi288EJ0M7NsP9fNgE7Qbg6ZfSce++n7QC7VuE=; b=h3RyNpi/m0ufDL7CxRqHiyx7xAaGEhfzmbVDpMEliNOGV96as2ntwUD7dP3kY3sYA9 daMOgfSGewshSq7dZ+skjt6gAAYqfy7JVQjjOiCrcQ4QFkiRQvxCeWXOAtU6SPcrh6hG JBpUbcabbCY+R69mBqBOBMEWhER8n9/6RZUyq7R1uaUCfDlrAm0ZrVUFTcj9BPYIiHoJ kr3RfQSThlBuLVRG6CdlCij0z+py2eptiaXrx4QkGDiSn/2o3qCnEmjsTkriZl2Fo5sn a+e8O+qKTVYvaks5avzwM988w0wRySPqvrwLMNKthmKKJYX615wHPBuY/Gdz8GwGVg2K cJZg== X-Gm-Message-State: AOAM5335aDC5R5hi8CfEs8cp47f8y3VE2e4shCwt4wOIbjnSG2Er6ihO LMBpYqQgZf3ghdqMsmhwsq7Ia7Nb5/ZG6lTYxatyzw== X-Google-Smtp-Source: ABdhPJzFb3M5KKDc0P6vzgQhF75tV/IB16cKzRo83AG6u77j3RQ1zLFiwZGnOCt2xN7WcZZR4msr6H1Iqkoxi26D0cs= X-Received: by 2002:a19:548:: with SMTP id 69mr2287824lff.465.1614865092582; Thu, 04 Mar 2021 05:38:12 -0800 (PST) MIME-Version: 1.0 References: <20210304034141.7062-1-brad@pensando.io> <20210304034141.7062-2-brad@pensando.io> <20210304091025.ny52qjm7wbfvmjgl@mobilestation> In-Reply-To: <20210304091025.ny52qjm7wbfvmjgl@mobilestation> From: Linus Walleij Date: Thu, 4 Mar 2021 14:38:01 +0100 Message-ID: Subject: Re: [PATCH 1/8] gpio: Add Elba SoC gpio driver for spi cs control To: Serge Semin Cc: Brad Larson , Linux ARM , Arnd Bergmann , Bartosz Golaszewski , Mark Brown , Adrian Hunter , Ulf Hansson , Olof Johansson , "open list:GPIO SUBSYSTEM" , linux-spi , linux-mmc , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "linux-kernel@vger.kernel.org" X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Mar 4, 2021 at 10:10 AM Serge Semin wrote: > On Thu, Mar 04, 2021 at 09:29:33AM +0100, Linus Walleij wrote: > > > + * pin: 3 2 | 1 0 > > > + * bit: 7------6------5------4----|---3------2------1------0 > > > + * cs1 cs1_ovr cs0 cs0_ovr | cs1 cs1_ovr cs0 cs0_ovr > > > + * ssi1 | ssi0 > > > + */ > > > +#define SPICS_PIN_SHIFT(pin) (2 * (pin)) > > > +#define SPICS_MASK(pin) (0x3 << SPICS_PIN_SHIFT(pin)) > > > +#define SPICS_SET(pin, val) ((((val) << 1) | 0x1) << SPICS_PIN_SHIFT(pin)) > > > > > So 2 bits per GPIO line in one register? (Nice doc!) > > I suppose the first bit is the CS-pin-override flag. So when it's set > the output is directly driven by the second bit, otherwise the > corresponding DW APB SPI controller drives it. That's how the > multiplexing is implemented here. If these output lines are so tightly coupled to the SPI block and will not be used for any other GPO (general purpose output) I think it makes more sense to bundle the handling into the DW SPI driver, and activate it based on the Elba compatible string (if of_is_compatible(...)). I am a bit cautious because it has happened in the past that people repurpose CS lines who were originally for SPI CS to all kind of other purposes, such as a power-on LED and in that case it needs to be a separate GPIO driver. So the author needs to have a good idea about what is a realistic use case here. Yours, Linus Walleij _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel