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h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=+Ead8LSWG66DphT0GLyzfFRHfp2cmEwD0BAU+nVi378=; b=pIFxq7Ix93yUv+EU9/GsxMJt/qpr+fxeFQ8fZah0ckentK6ra7V3ZWcuN6YGRR6aR1 PieKsSQmfE2klIM/yQI9RwxHUNBr3N0k/4rdFpx5x7qf6vz1XT6ZHSYjEyxmrpYzJpeS qeubUD68Ga4znF0Txw+BmrOai16owxMX1oYxJ8OFC7mXOxKfeozd9Gz9hI3MdK+KMP0H DUB7Aojx3jauKlxz2vLqbscUrLo2Y2zbXD2Ev5LUMOnkpAIg9hFuW3cIxW6IucyTUEwt 4iXPK65/hGCnZKk88qAld9TsiCtWUnj7gC0HNe6RFepIaL0cfgngW/bfxQBeBZe3fFqP DRjw== X-Gm-Message-State: AJcUukdsa/ufyrGl1WZOys3q2v252MhcO8tWANMGmm2lPdK9mpmTUGrs tPDMRHFHoWPb3KebpdZ2/i6vn/DajFlJRZdyCCl46DeHoKc= X-Google-Smtp-Source: ALg8bN6baeAcO2Y4iwM/cwg8J9P8BijOQY3CwAVhwt+ksxWZpz8UiiolIKzvyrOTOE/7W9qAXajM6tBeRvM5j8rK8JE= X-Received: by 2002:a19:41c4:: with SMTP id o187mr14614209lfa.32.1547479021918; Mon, 14 Jan 2019 07:17:01 -0800 (PST) MIME-Version: 1.0 References: <20190113095723.25295-1-wens@csie.org> <20190113095723.25295-2-wens@csie.org> In-Reply-To: <20190113095723.25295-2-wens@csie.org> From: Linus Walleij Date: Mon, 14 Jan 2019 16:16:50 +0100 Message-ID: Subject: Re: [PATCH v2 2/2] pinctrl: sunxi: Consider pin_base when calculating regulator array index To: Chen-Yu Tsai X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190114_071704_318397_E78F2EEF X-CRM114-Status: GOOD ( 13.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxime Ripard , "open list:GPIO SUBSYSTEM" , "linux-kernel@vger.kernel.org" , Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, Jan 13, 2019 at 10:57 AM Chen-Yu Tsai wrote: > On most newer Allwinner SoCs, there are two pinctrl devices, the PIO and > R_PIO. PIO covers pin-banks PA to PI (PJ and PK have not been seen), > while R_PIO covers PL to PN. The regulator array only has space for 12 > entries, which was designed to cover PA to PL. On the A80, the pin banks > go up to PN, which would be the 14th entry in the regulator array. > However since the driver only needs to track regulators for its own pin > banks, the array only needs to have 9 entries, and also take in to > account the value of pin_base, such that the regulator for the first > pin-bank of the pinctrl device, be it "PA" or "PL" uses the first entry > of the array. > > Base the regulator array index on pin_base, such that "PA" for PIO and > "PL" for R_PIO both take the first element within their respective > device's regulator array. > > Also decrease the size of the regulator array to 9, just enough to cover > "PA" to "PI". > > Fixes: 9a2a566adb00 ("pinctrl: sunxi: Deal with per-bank regulators") > Signed-off-by: Chen-Yu Tsai > --- > Changes since v1: > > - Take in to account pin_base when handling regulator array index > instead of enlarging the array to encompass PA - PN. Patch applied. Yours, Linus Walleij _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel