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[209.85.210.50]) by smtp.gmail.com with ESMTPSA id z20sm2391710otk.22.2019.11.08.15.48.54 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 08 Nov 2019 15:48:55 -0800 (PST) Received: by mail-ot1-f50.google.com with SMTP id t4so6720567otr.1 for ; Fri, 08 Nov 2019 15:48:54 -0800 (PST) X-Received: by 2002:a05:6830:17c2:: with SMTP id p2mr11400428ota.74.1573256934498; Fri, 08 Nov 2019 15:48:54 -0800 (PST) MIME-Version: 1.0 References: <20191108130123.6839-1-linux@rasmusvillemoes.dk> <20191108130123.6839-48-linux@rasmusvillemoes.dk> In-Reply-To: <20191108130123.6839-48-linux@rasmusvillemoes.dk> From: Li Yang Date: Fri, 8 Nov 2019 17:48:43 -0600 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 47/47] soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE To: Rasmus Villemoes X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191108_154857_193358_E0DBDCDB X-CRM114-Status: GOOD ( 17.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Christophe Leroy , lkml , Scott Wood , linuxppc-dev , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , Qiang Zhao Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Nov 8, 2019 at 7:05 AM Rasmus Villemoes wrote: > > There are also ARM and ARM64 based SOCs with a QUICC Engine, and the > core QE code as well as net/wan/fsl_ucc_hdlc and tty/serial/ucc_uart > has now been modified to not rely on ppcisms. > > So extend the architectures that can select QUICC_ENGINE, and add the > rather modest requirements of OF && HAS_IOMEM. > > The core code as well as the ucc_uart driver has been tested on an > LS1021A (arm), and it has also been tested that the QE code still > works on an mpc8309 (ppc). > > Signed-off-by: Rasmus Villemoes > --- > drivers/soc/fsl/qe/Kconfig | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig > index cfa4b2939992..f1974f811572 100644 > --- a/drivers/soc/fsl/qe/Kconfig > +++ b/drivers/soc/fsl/qe/Kconfig > @@ -5,7 +5,8 @@ > > config QUICC_ENGINE > bool "QUICC Engine (QE) framework support" > - depends on FSL_SOC && PPC32 > + depends on OF && HAS_IOMEM > + depends on PPC32 || ARM || ARM64 || COMPILE_TEST Can you also add PPC64? It is also used on some PPC64 platforms (QorIQ T series). > select GENERIC_ALLOCATOR > select CRC32 > help > -- > 2.23.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel