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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=yHFriWwVf2bpxF8jwq7dYnH8TViQ3A2S0W8/bFkGrXk=; b=Lx/5yJQg2ZizHM6qcuemCCgXFnUQ3XlW0MGrVYgRRp/Efj67oI9MEZUoHJJ/R9NQHK WhAcPJiQaklH3Pdvn75B6rKqY4twz2ucjc2DkcPEfgNW/DZkLKzuy6Oe7j5elcM0/HBY I2el6W2LLilbi0+XcDWJLoZvXmImPpFDMV7Sd9IBAOboKdjJWTrUII6y2+UjHPnRiGiu JL0oDeG8ovlu7t4l/uHovJ9SjLT/ChaoPp0iEUdWA/ltsH//A772oe7APr0mArpIbQIJ aGB8eVf8w8Px2kCEiidyYMmlz8wpXGLWP03S3cg2pAKn2J5qQy5Jqmp/iMiAvUqofLAH gTYw== X-Gm-Message-State: APjAAAUvC2GLagqPjiEul2f2SU4fYrIkyqbzFpfBlKdXfumYFSPUlogO FfBxdu/lnXXjdx0xjEjfynnlrkRv0ICi/k2KmEQ= X-Google-Smtp-Source: APXvYqzYQQrOqzq0lGlikGdKHOscdMMUlYZqW+h4DlZuPmBdDG28bYhGZKbxxSS7VizcvE2SXU3vAnQLc/C5vPctLEU= X-Received: by 2002:a92:d38e:: with SMTP id o14mr14108231ilo.238.1576251718323; Fri, 13 Dec 2019 07:41:58 -0800 (PST) MIME-Version: 1.0 References: <20191213074533.27048-1-maxime@cerno.tech> In-Reply-To: <20191213074533.27048-1-maxime@cerno.tech> From: Frank Lee Date: Fri, 13 Dec 2019 23:41:46 +0800 Message-ID: Subject: Re: [PATCH] dt-bindings: interconnect: Convert Allwinner MBUS controller to a schema To: Maxime Ripard X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191213_074159_921349_BDE0605F X-CRM114-Status: GOOD ( 20.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree , Linux PM , Maxime Ripard , Chen-Yu Tsai , Rob Herring , Frank Rowand , georgi.djakov@linaro.org, Linux ARM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Dec 13, 2019 at 3:45 PM Maxime Ripard wrote: > > The older Allwinner SoCs have an MBUS controller that is used by Linux, > with a matching Device Tree binding. > > Now that we have the DT validation in place, let's convert the device tree > bindings for that controller over to a YAML schemas. > > Signed-off-by: Maxime Ripard > --- > .../arm/sunxi/allwinner,sun4i-a10-mbus.yaml | 65 +++++++++++++++++++ > .../bindings/arm/sunxi/sunxi-mbus.txt | 37 ----------- > 2 files changed, 65 insertions(+), 37 deletions(-) > create mode 100644 Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml > delete mode 100644 Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt > > diff --git a/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml > new file mode 100644 > index 000000000000..9370e64992dd > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/sunxi/allwinner,sun4i-a10-mbus.yaml > @@ -0,0 +1,65 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/sunxi/allwinner,sun4i-a10-mbus.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Allwinner Memory Bus (MBUS) controller > + > +maintainers: > + - Chen-Yu Tsai > + - Maxime Ripard > + > +description: | > + The MBUS controller drives the MBUS that other devices in the SoC > + will use to perform DMA. It also has a register interface that > + allows to monitor and control the bandwidth and priorities for > + masters on that bus. > + > + Each device having to perform their DMA through the MBUS must have > + the interconnects and interconnect-names properties set to the MBUS > + controller and with "dma-mem" as the interconnect name. > + > +properties: > + "#interconnect-cells": > + const: 1 > + description: > + The content of the cell is the MBUS ID. > + > + compatible: > + enum: > + - allwinner,sun5i-a13-mbus > + - allwinner,sun8i-h3-mbus Is there a driver in mainline for it? Thx, Yangtao > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + dma-ranges: > + description: > + See section 2.3.9 of the DeviceTree Specification. > + > +required: > + - "#interconnect-cells" > + - compatible > + - reg > + - clocks > + - dma-ranges > + > +additionalProperties: false > + > +examples: > + - | > + #include > + > + mbus: dram-controller@1c01000 { > + compatible = "allwinner,sun5i-a13-mbus"; > + reg = <0x01c01000 0x1000>; > + clocks = <&ccu CLK_MBUS>; > + dma-ranges = <0x00000000 0x40000000 0x20000000>; > + #interconnect-cells = <1>; > + }; > + > +... > diff --git a/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt b/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt > deleted file mode 100644 > index 2005bb486705..000000000000 > --- a/Documentation/devicetree/bindings/arm/sunxi/sunxi-mbus.txt > +++ /dev/null > @@ -1,37 +0,0 @@ > -Allwinner Memory Bus (MBUS) controller > - > -The MBUS controller drives the MBUS that other devices in the SoC will > -use to perform DMA. It also has a register interface that allows to > -monitor and control the bandwidth and priorities for masters on that > -bus. > - > -Required properties: > - - compatible: Must be one of: > - - allwinner,sun5i-a13-mbus > - - allwinner,sun8i-h3-mbus > - - reg: Offset and length of the register set for the controller > - - clocks: phandle to the clock driving the controller > - - dma-ranges: See section 2.3.9 of the DeviceTree Specification > - - #interconnect-cells: Must be one, with the argument being the MBUS > - port ID > - > -Each device having to perform their DMA through the MBUS must have the > -interconnects and interconnect-names properties set to the MBUS > -controller and with "dma-mem" as the interconnect name. > - > -Example: > - > -mbus: dram-controller@1c01000 { > - compatible = "allwinner,sun5i-a13-mbus"; > - reg = <0x01c01000 0x1000>; > - clocks = <&ccu CLK_MBUS>; > - dma-ranges = <0x00000000 0x40000000 0x20000000>; > - #interconnect-cells = <1>; > -}; > - > -fe0: display-frontend@1e00000 { > - compatible = "allwinner,sun5i-a13-display-frontend"; > - ... > - interconnects = <&mbus 19>; > - interconnect-names = "dma-mem"; > -}; > -- > 2.23.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel