From: Rob Clark <robdclark@gmail.com>
To: Will Deacon <will@kernel.org>
Cc: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>,
Robin Murphy <robin.murphy@arm.com>,
Joerg Roedel <joro@8bytes.org>,
Akhil P Oommen <akhilpo@codeaurora.org>,
"Isaac J. Manjarres" <isaacm@codeaurora.org>,
"list@263.net:IOMMU DRIVERS , Joerg Roedel <joro@8bytes.org>,
" <iommu@lists.linux-foundation.org>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-arm-msm <linux-arm-msm@vger.kernel.org>,
freedreno <freedreno@lists.freedesktop.org>,
Kristian H Kristensen <hoegsberg@google.com>,
Sean Paul <sean@poorly.run>, David Airlie <airlied@linux.ie>,
Daniel Vetter <daniel@ffwll.ch>,
dri-devel <dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH 2/3] iommu/io-pgtable-arm: Add IOMMU_LLC page protection flag
Date: Tue, 16 Mar 2021 10:16:31 -0700 [thread overview]
Message-ID: <CAF6AEGuc5i9hMtfU3HSpLVWi_e=emJTPLqntzJfAH69dO_gagA@mail.gmail.com> (raw)
In-Reply-To: <CAF6AEGveB=t0gQ0-WZn_qy=scYR60DEcum53saovg5h31ZMHog@mail.gmail.com>
On Tue, Mar 16, 2021 at 10:04 AM Rob Clark <robdclark@gmail.com> wrote:
>
> On Wed, Feb 3, 2021 at 2:14 PM Rob Clark <robdclark@gmail.com> wrote:
> >
> > On Wed, Feb 3, 2021 at 1:46 PM Will Deacon <will@kernel.org> wrote:
> > >
> > > On Tue, Feb 02, 2021 at 11:56:27AM +0530, Sai Prakash Ranjan wrote:
> > > > On 2021-02-01 23:50, Jordan Crouse wrote:
> > > > > On Mon, Feb 01, 2021 at 08:20:44AM -0800, Rob Clark wrote:
> > > > > > On Mon, Feb 1, 2021 at 3:16 AM Will Deacon <will@kernel.org> wrote:
> > > > > > > On Fri, Jan 29, 2021 at 03:12:59PM +0530, Sai Prakash Ranjan wrote:
> > > > > > > > On 2021-01-29 14:35, Will Deacon wrote:
> > > > > > > > > On Mon, Jan 11, 2021 at 07:45:04PM +0530, Sai Prakash Ranjan wrote:
> > > > > > > > > > +#define IOMMU_LLC (1 << 6)
> > > > > > > > >
> > > > > > > > > On reflection, I'm a bit worried about exposing this because I think it
> > > > > > > > > will
> > > > > > > > > introduce a mismatched virtual alias with the CPU (we don't even have a
> > > > > > > > > MAIR
> > > > > > > > > set up for this memory type). Now, we also have that issue for the PTW,
> > > > > > > > > but
> > > > > > > > > since we always use cache maintenance (i.e. the streaming API) for
> > > > > > > > > publishing the page-tables to a non-coheren walker, it works out.
> > > > > > > > > However,
> > > > > > > > > if somebody expects IOMMU_LLC to be coherent with a DMA API coherent
> > > > > > > > > allocation, then they're potentially in for a nasty surprise due to the
> > > > > > > > > mismatched outer-cacheability attributes.
> > > > > > > > >
> > > > > > > >
> > > > > > > > Can't we add the syscached memory type similar to what is done on android?
> > > > > > >
> > > > > > > Maybe. How does the GPU driver map these things on the CPU side?
> > > > > >
> > > > > > Currently we use writecombine mappings for everything, although there
> > > > > > are some cases that we'd like to use cached (but have not merged
> > > > > > patches that would give userspace a way to flush/invalidate)
> > > > > >
> > > > >
> > > > > LLC/system cache doesn't have a relationship with the CPU cache. Its
> > > > > just a
> > > > > little accelerator that sits on the connection from the GPU to DDR and
> > > > > caches
> > > > > accesses. The hint that Sai is suggesting is used to mark the buffers as
> > > > > 'no-write-allocate' to prevent GPU write operations from being cached in
> > > > > the LLC
> > > > > which a) isn't interesting and b) takes up cache space for read
> > > > > operations.
> > > > >
> > > > > Its easiest to think of the LLC as a bonus accelerator that has no cost
> > > > > for
> > > > > us to use outside of the unfortunate per buffer hint.
> > > > >
> > > > > We do have to worry about the CPU cache w.r.t I/O coherency (which is a
> > > > > different hint) and in that case we have all of concerns that Will
> > > > > identified.
> > > > >
> > > >
> > > > For mismatched outer cacheability attributes which Will mentioned, I was
> > > > referring to [1] in android kernel.
> > >
> > > I've lost track of the conversation here :/
> > >
> > > When the GPU has a buffer mapped with IOMMU_LLC, is the buffer also mapped
> > > into the CPU and with what attributes? Rob said "writecombine for
> > > everything" -- does that mean ioremap_wc() / MEMREMAP_WC?
> >
> > Currently userspace asks for everything WC, so pgprot_writecombine()
> >
> > The kernel doesn't enforce this, but so far provides no UAPI to do
> > anything useful with non-coherent cached mappings (although there is
> > interest to support this)
> >
>
> btw, I'm looking at a benchmark (gl_driver2_off) where (after some
> other in-flight optimizations land) we end up bottlenecked on writing
> to WC cmdstream buffers. I assume in the current state, WC goes all
> the way to main memory rather than just to system cache?
>
oh, I guess this (mentioned earlier in thread) is what I really want
for this benchmark:
https://android-review.googlesource.com/c/kernel/common/+/1549097/3
> BR,
> -R
>
> > BR,
> > -R
> >
> > > Finally, we need to be careful when we use the word "hint" as "allocation
> > > hint" has a specific meaning in the architecture, and if we only mismatch on
> > > those then we're actually ok. But I think IOMMU_LLC is more than just a
> > > hint, since it actually drives eviction policy (i.e. it enables writeback).
> > >
> > > Sorry for the pedantry, but I just want to make sure we're all talking
> > > about the same things!
> > >
> > > Cheers,
> > >
> > > Will
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next prev parent reply other threads:[~2021-03-16 17:15 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <cover.1610372717.git.saiprakash.ranjan@codeaurora.org>
[not found] ` <3f589e7de3f9fa93e84c83420c5270c546a0c368.1610372717.git.saiprakash.ranjan@codeaurora.org>
2021-01-29 9:05 ` [PATCH 2/3] iommu/io-pgtable-arm: Add IOMMU_LLC page protection flag Will Deacon
[not found] ` <5d23fce629323bcda71594010824aad0@codeaurora.org>
2021-02-01 11:15 ` Will Deacon
2021-02-01 16:20 ` Rob Clark
[not found] ` <20210201182016.GA21629@jcrouse1-lnx.qualcomm.com>
[not found] ` <7e9aade14d0b7f69285852ade4a5a9f4@codeaurora.org>
2021-02-03 21:46 ` Will Deacon
2021-02-03 22:14 ` Rob Clark
2021-03-16 17:04 ` Rob Clark
2021-03-16 17:16 ` Rob Clark [this message]
[not found] ` <4988e2ef35f76a0c2f1fe3f66f023a3b@codeaurora.org>
[not found] ` <9362873a3bcf37cdd073a6128f29c683@codeaurora.org>
2021-03-25 17:33 ` Will Deacon
2021-07-28 14:00 ` [PATCH 0/3] iommu/drm/msm: Allow non-coherent masters to use system cache Georgi Djakov
[not found] ` <8b2742c8891abe4fec3664730717a089@codeaurora.org>
2021-08-02 10:55 ` Will Deacon
2021-08-02 15:08 ` [Freedreno] " Rob Clark
2021-08-02 15:14 ` Will Deacon
2021-08-03 1:36 ` Rob Clark
2021-08-09 14:56 ` Will Deacon
2021-08-09 16:57 ` Rob Clark
2021-08-09 17:05 ` Will Deacon
2021-08-09 17:18 ` Rob Clark
2021-08-09 17:40 ` Will Deacon
[not found] ` <76bfd0b4248148dfbf9d174ddcb4c2a2@codeaurora.org>
2021-08-09 18:07 ` Rob Clark
[not found] ` <8e5edd6886a0c3a5f6c8cb4dff517224@codeaurora.org>
2021-08-09 18:30 ` Rob Clark
2021-08-10 9:16 ` Will Deacon
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