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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=tJhKCSfHKsoJq4+iPmQ+CTnGGZoUh1cxbcC3UfHyjno=; b=iq9KeRr/tnMNzH8AWf4rb3dARzRoDOqxcmXDwXk2aMYTZ/WLx4t9z5pYhWiX432/Og uoHL0wi45BtS8K3uFXozF7iuBwj67wkM+4amW2ZIXzripjh/Y0/0NOOImF1tGECqN+dl h+DdAsv6IrnIaWJNfKFPYvWvh18HFeJRrP2Ul1kFST2A/6xY3ZeooPEsqN0SEoRhhGpH 66z2nOc6pyNBkb3UZu2ElCRK5XmKIq3mwSzjjpAnaSyU7wvzoNoaor+888O7sYteF00I xo24TuvF+GyKZbiYAq+/5na0LPDYwwdcxQS4ECdGAe2Tt1oNN+BO4OXgLCta9m61xUGU h2LQ== X-Gm-Message-State: AOAM533yF9VeVuJIci/OS4fOo8XnocLCkqnV6RSJ+2coduI6gpIfEn4C gGOeWhCS6NSqnI7OTMM/20gS3Q/OXykWnzV+4Mo= X-Google-Smtp-Source: ABdhPJxL2gSk8Byau/BSY6kZmFScPsa7g6bppC6AWZ9vfbc8KmC0NMwTfuPXPyOCy48yyEb+BQYtGIYgo+5gQhtG7do= X-Received: by 2002:a17:906:494a:: with SMTP id f10mr60249442ejt.428.1594313759675; Thu, 09 Jul 2020 09:55:59 -0700 (PDT) MIME-Version: 1.0 References: <20200709050145.3520931-1-bjorn.andersson@linaro.org> <20200709050145.3520931-3-bjorn.andersson@linaro.org> <20200709164833.GR11847@yoga> In-Reply-To: <20200709164833.GR11847@yoga> From: Rob Clark Date: Thu, 9 Jul 2020 09:56:31 -0700 Message-ID: Subject: Re: [PATCH 2/5] iommu/arm-smmu: Emulate bypass by using context banks To: Bjorn Andersson X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200709_125601_542030_12A81A90 X-CRM114-Status: GOOD ( 26.40 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jonathan Marek , Will Deacon , Joerg Roedel , Linux Kernel Mailing List , "list@263.net:IOMMU DRIVERS , Joerg Roedel , " , Thierry Reding , linux-arm-msm , Robin Murphy , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , Laurentiu Tudor Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jul 9, 2020 at 9:48 AM Bjorn Andersson wrote: > > On Thu 09 Jul 09:17 PDT 2020, Rob Clark wrote: > > > On Wed, Jul 8, 2020 at 10:01 PM Bjorn Andersson > > wrote: > [..] > > > @@ -678,7 +680,11 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, > > > if (smmu_domain->smmu) > > > goto out_unlock; > > > > > > - if (domain->type == IOMMU_DOMAIN_IDENTITY) { > > > + /* > > > + * Nothing to do for IDENTITY domains,unless disabled context banks are > > > + * used to emulate bypass mappings on Qualcomm platforms. > > > + */ > > > + if (domain->type == IOMMU_DOMAIN_IDENTITY && !smmu->qcom_bypass_quirk) { > > > > maybe I'm overlooking something, but I think this would put us back to > > allocating pgtables (and making iommu->map/unmap() no longer no-ops), > > which I don't think we want > > > > You're right, we are allocating page tables for these contexts and > map/unmap would modify the page tables. But afaict traversal is never > performed, given that the banks are never enabled. > > But as drivers probe properly, or the direct mapped drivers sets up > their iommu domains explicitly with translation this would not be used. > > So afaict we're just wasting some memory - for the gain of not > overcomplicating this function. the problem is that it makes dma_map/unmap less of a no-op than it should be (for the case where the driver is explicitly managing it's own domain).. I was hoping to get rid of the hacks to use dma_sync go back to dma_map/unmap for cache cleaning BR, -R > > Regards, > Bjorn > > > BR, > > -R > > > > > smmu_domain->stage = ARM_SMMU_DOMAIN_BYPASS; > > > smmu_domain->smmu = smmu; > > > goto out_unlock; > > > @@ -826,6 +832,10 @@ static int arm_smmu_init_domain_context(struct iommu_domain *domain, > > > domain->geometry.aperture_end = (1UL << ias) - 1; > > > domain->geometry.force_aperture = true; > > > > > > + /* Enable translation for non-identity context banks */ > > > + if (domain->type != IOMMU_DOMAIN_IDENTITY) > > > + cfg->m = true; > > > + > > > /* Initialise the context bank with our page table cfg */ > > > arm_smmu_init_context_bank(smmu_domain, &pgtbl_cfg); > > > arm_smmu_write_context_bank(smmu, cfg->cbndx); > > > diff --git a/drivers/iommu/arm-smmu.h b/drivers/iommu/arm-smmu.h > > > index d172c024be61..a71d193073e4 100644 > > > --- a/drivers/iommu/arm-smmu.h > > > +++ b/drivers/iommu/arm-smmu.h > > > @@ -305,6 +305,8 @@ struct arm_smmu_device { > > > > > > /* IOMMU core code handle */ > > > struct iommu_device iommu; > > > + > > > + bool qcom_bypass_quirk; > > > }; > > > > > > enum arm_smmu_context_fmt { > > > @@ -323,6 +325,7 @@ struct arm_smmu_cfg { > > > }; > > > enum arm_smmu_cbar_type cbar; > > > enum arm_smmu_context_fmt fmt; > > > + bool m; > > > }; > > > #define ARM_SMMU_INVALID_IRPTNDX 0xff > > > > > > -- > > > 2.26.2 > > > > > > _______________________________________________ > > > iommu mailing list > > > iommu@lists.linux-foundation.org > > > https://lists.linuxfoundation.org/mailman/listinfo/iommu _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel