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From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: Jerome Brunet <jbrunet@baylibre.com>
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
	Neil Armstrong <narmstrong@baylibre.com>,
	khilman@baylibre.com, linux-kernel@vger.kernel.org,
	robh+dt@kernel.org, linux-amlogic@lists.infradead.org,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 0/6] add the DDR clock controller on Meson8 and Meson8b
Date: Mon, 23 Sep 2019 22:49:37 +0200	[thread overview]
Message-ID: <CAFBinCAHD+D=a2mHeHMGq12MvoksHBr308jSrdcH+UYsUmwd8w@mail.gmail.com> (raw)
In-Reply-To: <1jsgons4wy.fsf@starbuckisacylon.baylibre.com>

Hi Jerome,

On Mon, Sep 23, 2019 at 12:06 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
>
> On Sat 21 Sep 2019 at 17:18, Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:
>
> > Meson8 and Meson8b SoCs embed a DDR clock controller in their MMCBUS
> > registers. This series:
> > - adds support for this DDR clock controller (patches 0 and 1)
> > - wires up the DDR PLL as input for two audio clocks (patches 2 and 3)
>
> Have you been able to validate somehow that DDR rate calculated by CCF
> is the actual rate that gets to the audio clocks ?
no, I haven't been able to validate this (yet)

> While I understand the interest for completeness, I suspect the having
> the DDR clock as an audio parent was just for debugging purpose. IOW,
> I'm not sure if adding this parent is useful to an actual audio use
> case. As far as audio would be concerned, I think we are better of
> without this parent.
there at least three other (potential) consumers of the ddr_pll clocks
on the 32-bit SoCs:
- CPU clock mux [0]
- clk81 mux [1]
- USB PHY [2]

I have not validated any of these either

> > - adds the DDR clock controller to meson8.dtsi and meson8b.dtsi
> >
>
> Could you please separate the driver and DT series in the future ? Those
> take different paths and are meant for different maintainers.
sure - so far Kevin has been doing a great job of still tracking these
but I'm happy to split this into two patchsets


Martin


[0] https://github.com/endlessm/u-boot-meson/blob/345ee7eb02903f5ecb1173ffb2cd36666e44ebed/board/amlogic/m8b_m201_v1/firmware/timming.c#L441
[1] https://github.com/endlessm/u-boot-meson/blob/345ee7eb02903f5ecb1173ffb2cd36666e44ebed/board/amlogic/m8b_m201_v1/firmware/timming.c#L452
[2] https://github.com/endlessm/u-boot-meson/blob/f1ee03e3f7547d03e1478cc1fc967a9e5a121d92/arch/arm/cpu/aml_meson/m8/firmware/usb_boot/platform.c#L22

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  reply	other threads:[~2019-09-23 20:50 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-21 15:18 [PATCH 0/6] add the DDR clock controller on Meson8 and Meson8b Martin Blumenstingl
2019-09-21 15:18 ` [PATCH 1/6] dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding Martin Blumenstingl
2019-10-02 14:19   ` Rob Herring
2019-09-21 15:18 ` [PATCH 2/6] clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller Martin Blumenstingl
2019-10-01 13:29   ` Jerome Brunet
2019-10-01 18:53     ` Martin Blumenstingl
2019-10-02  9:04       ` Jerome Brunet
2019-09-21 15:18 ` [PATCH 3/6] clk: meson: meson8b: use of_clk_hw_register to register the clocks Martin Blumenstingl
2019-09-21 15:18 ` [PATCH 4/6] clk: meson: meson8b: add the ddr_pll input for the audio clocks Martin Blumenstingl
2019-09-21 15:18 ` [PATCH 5/6] ARM: dts: meson8: add the DDR clock controller Martin Blumenstingl
2019-09-21 15:18 ` [PATCH 6/6] ARM: dts: meson8b: " Martin Blumenstingl
2019-09-23 10:06 ` [PATCH 0/6] add the DDR clock controller on Meson8 and Meson8b Jerome Brunet
2019-09-23 20:49   ` Martin Blumenstingl [this message]
2019-10-01 13:33     ` Jerome Brunet

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