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Tue, 18 May 2021 13:21:08 -0700 (PDT) MIME-Version: 1.0 References: <20210517203724.1006254-1-martin.blumenstingl@googlemail.com> <1jwnrw1ohh.fsf@starbuckisacylon.baylibre.com> In-Reply-To: <1jwnrw1ohh.fsf@starbuckisacylon.baylibre.com> From: Martin Blumenstingl Date: Tue, 18 May 2021 22:20:57 +0200 Message-ID: Subject: Re: [PATCH RFC v1 0/3] clk: meson: rounding for fast clocks on 32-bit SoCs To: Jerome Brunet Cc: mturquette@baylibre.com, sboyd@kernel.org, Neil Armstrong , linux-clk@vger.kernel.org, khilman@baylibre.com, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210518_132109_771332_D7EE5245 X-CRM114-Status: GOOD ( 21.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Jerome, On Tue, May 18, 2021 at 9:37 AM Jerome Brunet wrote: > > > On Mon 17 May 2021 at 22:37, Martin Blumenstingl wrote: > > > On the 32-bit Amlogic Meson8/8b/8m2 SoCs we run into a problem with the > > fast HDMI PLL and it's OD (post-dividers). This clock tree can run at > > up to approx. 3GHz. > > This however causes a problem, because these rates require BIT(31) to > > be usable. Unfortunately this is not the case with clk_ops.round_rate > > on 32-bit systems. BIT(31) is reserved for the sign (+ or -). > > > > clk_ops.determine_rate does not suffer from this limitation. It uses > > an int to signal any errors and can then take all availble 32 bits for > > the clock rate. > > > > I am sending this as RFC to start a discussion whether: > > - this is a good way to solve it? > > .determine_rate() was meant to replace .round_rate() so I guess it is > good to do it :) ah, now things make more sense. thanks for the background info > > - what are the alternatives? > > I don't see any ATM. Even with determine_rate(), 4.29GHz limitation > seems a bit low nowadays. In AML SoC, most PLLs should be able to reach > 6GHz ... hopefully we won't need that on the 32bits variant ;) according to the public datasheet the maximum PLL frequency is at around 3GHz so I also hope that we're safe with this Martin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel