linux-arm-kernel.lists.infradead.org archive mirror
 help / color / mirror / Atom feed
From: Enric Balletbo Serra <eballetbo@gmail.com>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Heiko Stuebner <heiko@sntech.de>,
	Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>,
	linux-pci@vger.kernel.org,
	Linus Walleij <linus.walleij@linaro.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
	Toan Le <toan@os.amperecomputing.com>,
	Will Deacon <will@kernel.org>, Rob Herring <robh@kernel.org>,
	Ryder Lee <ryder.lee@mediatek.com>,
	Michal Simek <michal.simek@xilinx.com>,
	Christoph Hellwig <hch@infradead.org>,
	"open list:ARM/Rockchip SoC..."
	<linux-rockchip@lists.infradead.org>,
	bcm-kernel-feedback-list@broadcom.com,
	Shawn Lin <shawn.lin@rock-chips.com>, Ray Jui <rjui@broadcom.com>,
	Hou Zhiqiang <Zhiqiang.Hou@nxp.com>,
	Simon Horman <horms@verge.net.au>,
	"moderated list:ARM/Mediatek SoC support"
	<linux-mediatek@lists.infradead.org>,
	Andrew Murray <andrew.murray@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>,
	Scott Branden <sbranden@broadcom.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	rfi@lists.rocketboards.org, linux-renesas-soc@vger.kernel.org,
	Tom Joseph <tjoseph@cadence.com>,
	Srinath Mannam <srinath.mannam@broadcom.com>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Ley Foon Tan <lftan@altera.com>
Subject: Re: [PATCH v3 11/25] PCI: rockchip: Drop storing driver private outbound resource data
Date: Tue, 10 Dec 2019 18:33:36 +0100	[thread overview]
Message-ID: <CAFqH_53nX74vD6-T2ao0x540wq_NbN671H5i2fwbo6NaCgc4KQ@mail.gmail.com> (raw)
In-Reply-To: <20191206153633.GA18142@e121166-lin.cambridge.arm.com>

Hi Lorenzo,

Many thanks to look at this.

Missatge de Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> del dia dv.,
6 de des. 2019 a les 16:36:
>
> [+Eric]
>
> On Mon, Oct 28, 2019 at 11:32:42AM -0500, Rob Herring wrote:
> > The Rockchip host bridge driver doesn't need to store outboard resources
> > in its private struct as they are already stored in struct
> > pci_host_bridge.
> >
> > Cc: Shawn Lin <shawn.lin@rock-chips.com>
> > Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > Cc: Andrew Murray <andrew.murray@arm.com>
> > Cc: Bjorn Helgaas <bhelgaas@google.com>
> > Cc: Heiko Stuebner <heiko@sntech.de>
> > Cc: linux-rockchip@lists.infradead.org
> > Signed-off-by: Rob Herring <robh@kernel.org>
> > ---
> >  drivers/pci/controller/pcie-rockchip-host.c | 54 +++++++++------------
> >  drivers/pci/controller/pcie-rockchip.h      |  5 --
> >  2 files changed, 23 insertions(+), 36 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
> > index 8d2e6f2e141e..f375e55ea02e 100644
> > --- a/drivers/pci/controller/pcie-rockchip-host.c
> > +++ b/drivers/pci/controller/pcie-rockchip-host.c
> > @@ -806,19 +806,28 @@ static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
> >  static int rockchip_pcie_cfg_atu(struct rockchip_pcie *rockchip)
> >  {
> >       struct device *dev = rockchip->dev;
> > +     struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rockchip);
> > +     struct resource_entry *entry;
> > +     u64 pci_addr, size;
> >       int offset;
> >       int err;
> >       int reg_no;
> >
> >       rockchip_pcie_cfg_configuration_accesses(rockchip,
> >                                                AXI_WRAPPER_TYPE0_CFG);
> > +     entry = resource_list_first_type(&bridge->windows, IORESOURCE_MEM);
> > +     if (!entry)
> > +             return -ENODEV;
> > +
> > +     size = resource_size(entry->res);
> > +     pci_addr = entry->res->start - entry->offset;
> > +     rockchip->msg_bus_addr = pci_addr;
> >
> > -     for (reg_no = 0; reg_no < (rockchip->mem_size >> 20); reg_no++) {
> > +     for (reg_no = 0; reg_no < (size >> 20); reg_no++) {
> >               err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1,
> >                                               AXI_WRAPPER_MEM_WRITE,
> >                                               20 - 1,
> > -                                             rockchip->mem_bus_addr +
> > -                                             (reg_no << 20),
> > +                                             pci_addr + (reg_no << 20),
> >                                               0);
> >               if (err) {
> >                       dev_err(dev, "program RC mem outbound ATU failed\n");
> > @@ -832,14 +841,20 @@ static int rockchip_pcie_cfg_atu(struct rockchip_pcie *rockchip)
> >               return err;
> >       }
> >
> > -     offset = rockchip->mem_size >> 20;
> > -     for (reg_no = 0; reg_no < (rockchip->io_size >> 20); reg_no++) {
> > +     entry = resource_list_first_type(&bridge->windows, IORESOURCE_IO);
> > +     if (!entry)
> > +             return -ENODEV;
> > +
> > +     size = resource_size(entry->res);
> > +     pci_addr = entry->res->start - entry->offset;
> > +
> > +     offset = size >> 20;
>
> Just trying to find what triggers:
>
> https://lore.kernel.org/linux-pci/CAFqH_52BiQJzNEzd_0pB3K+JmzVOVikYQo0xfiC0J-DwiXdtqw@mail.gmail.com/T/#u
>
> I think this offset calculation changed the behaviour:
>
> Before:
>
> > -     offset = rockchip->mem_size >> 20;
>
> Now:
>
> > +     offset = size >> 20;
>
> size must be the IORESOURCE_MEM resource size instead we are using the
> IORESOURCE_IO size so IIUC the ATU window setup may be compromised.
>

Are you suggesting that something like this [1] fixes the issue?

Indeed,I don't see the warning with this applied and wifi which is
connected via pcie is working. But I don't get why the offset should
be from the MEM resource instead of the IO resource.

[1] https://pastebin.com/FBj95gNR

Thanks,
 Enric

> Lorenzo
>
> > +     for (reg_no = 0; reg_no < (size >> 20); reg_no++) {
> >               err = rockchip_pcie_prog_ob_atu(rockchip,
> >                                               reg_no + 1 + offset,
> >                                               AXI_WRAPPER_IO_WRITE,
> >                                               20 - 1,
> > -                                             rockchip->io_bus_addr +
> > -                                             (reg_no << 20),
> > +                                             pci_addr + (reg_no << 20),
> >                                               0);
> >               if (err) {
> >                       dev_err(dev, "program RC io outbound ATU failed\n");
> > @@ -852,8 +867,7 @@ static int rockchip_pcie_cfg_atu(struct rockchip_pcie *rockchip)
> >                                 AXI_WRAPPER_NOR_MSG,
> >                                 20 - 1, 0, 0);
> >
> > -     rockchip->msg_bus_addr = rockchip->mem_bus_addr +
> > -                                     ((reg_no + offset) << 20);
> > +     rockchip->msg_bus_addr += ((reg_no + offset) << 20);
> >       return err;
> >  }
> >
> > @@ -951,7 +965,6 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
> >       struct pci_bus *bus, *child;
> >       struct pci_host_bridge *bridge;
> >       struct resource *bus_res;
> > -     struct resource_entry *win;
> >       int err;
> >
> >       if (!dev->of_node)
> > @@ -997,27 +1010,6 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
> >
> >       rockchip->root_bus_nr = bus_res->start;
> >
> > -     /* Get the I/O and memory ranges from DT */
> > -     resource_list_for_each_entry(win, &bridge->windows) {
> > -             switch (resource_type(win->res)) {
> > -             case IORESOURCE_IO:
> > -                     io = win->res;
> > -                     io->name = "I/O";
> > -                     rockchip->io_size = resource_size(io);
> > -                     rockchip->io_bus_addr = io->start - win->offset;
> > -                     rockchip->io = io;
> > -                     break;
> > -             case IORESOURCE_MEM:
> > -                     mem = win->res;
> > -                     mem->name = "MEM";
> > -                     rockchip->mem_size = resource_size(mem);
> > -                     rockchip->mem_bus_addr = mem->start - win->offset;
> > -                     break;
> > -             default:
> > -                     continue;
> > -             }
> > -     }
> > -
> >       err = rockchip_pcie_cfg_atu(rockchip);
> >       if (err)
> >               goto err_remove_irq_domain;
> > diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h
> > index 8e87a059ce73..bef42a803b56 100644
> > --- a/drivers/pci/controller/pcie-rockchip.h
> > +++ b/drivers/pci/controller/pcie-rockchip.h
> > @@ -304,13 +304,8 @@ struct rockchip_pcie {
> >       struct  irq_domain *irq_domain;
> >       int     offset;
> >       struct pci_bus *root_bus;
> > -     struct resource *io;
> > -     phys_addr_t io_bus_addr;
> > -     u32     io_size;
> >       void    __iomem *msg_region;
> > -     u32     mem_size;
> >       phys_addr_t msg_bus_addr;
> > -     phys_addr_t mem_bus_addr;
> >       bool is_rc;
> >       struct resource *mem_res;
> >  };
> > --
> > 2.20.1
> >

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2019-12-10 17:33 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-28 16:32 [PATCH v3 00/25] PCI host resource consolidation Rob Herring
2019-10-28 16:32 ` [PATCH v3 01/25] resource: Add a resource_list_first_type helper Rob Herring
2019-10-28 16:32 ` [PATCH v3 02/25] PCI: Export pci_parse_request_of_pci_ranges() Rob Herring
2019-10-28 16:32 ` [PATCH v3 03/25] PCI: aardvark: Use pci_parse_request_of_pci_ranges() Rob Herring
2019-10-28 16:32 ` [PATCH v3 04/25] PCI: altera: " Rob Herring
2019-10-28 16:32 ` [PATCH v3 05/25] PCI: dwc: " Rob Herring
2019-10-28 16:32 ` [PATCH v3 06/25] PCI: faraday: " Rob Herring
2019-11-03 19:12   ` Linus Walleij
2019-10-28 16:32 ` [PATCH v3 07/25] PCI: iproc: " Rob Herring
2019-10-29 15:58   ` Srinath Mannam
2019-10-29 17:09     ` Florian Fainelli
2019-10-28 16:32 ` [PATCH v3 08/25] PCI: mediatek: " Rob Herring
2019-10-28 16:32 ` [PATCH v3 09/25] PCI: mobiveil: " Rob Herring
2019-10-29  9:00   ` Z.q. Hou
2019-10-28 16:32 ` [PATCH v3 10/25] PCI: rockchip: " Rob Herring
2019-12-05 17:56   ` Enric Balletbo Serra
2019-12-06 13:52     ` Lorenzo Pieralisi
2019-12-06 14:09     ` Lorenzo Pieralisi
2019-12-06 14:59       ` Enric Balletbo Serra
2019-10-28 16:32 ` [PATCH v3 11/25] PCI: rockchip: Drop storing driver private outbound resource data Rob Herring
2019-12-06 15:36   ` Lorenzo Pieralisi
2019-12-10 17:33     ` Enric Balletbo Serra [this message]
2019-12-11  9:39       ` Enric Balletbo Serra
2019-10-28 16:32 ` [PATCH v3 12/25] PCI: v3-semi: Use pci_parse_request_of_pci_ranges() Rob Herring
2019-10-28 16:32 ` [PATCH v3 13/25] PCI: xgene: " Rob Herring
2019-10-28 16:32 ` [PATCH v3 14/25] PCI: xilinx: " Rob Herring
2019-10-28 16:32 ` [PATCH v3 15/25] PCI: xilinx-nwl: " Rob Herring
2019-10-28 16:32 ` [PATCH v3 16/25] PCI: versatile: " Rob Herring
2019-10-28 16:32 ` [PATCH v3 17/25] PCI: versatile: Remove usage of PHYS_OFFSET Rob Herring
2019-10-28 16:32 ` [PATCH v3 18/25] PCI: versatile: Enable COMPILE_TEST Rob Herring
2019-10-28 16:32 ` [PATCH v3 19/25] PCI: of: Add inbound resource parsing to helpers Rob Herring
2019-10-29 11:07   ` Lorenzo Pieralisi
2019-10-29 15:56     ` Srinath Mannam
2019-10-29 17:34       ` Lorenzo Pieralisi
2019-10-30  6:44         ` Srinath Mannam
2019-10-30 11:48           ` Lorenzo Pieralisi
2019-10-30 12:49             ` Robin Murphy
2019-10-30 14:56               ` Lorenzo Pieralisi
2019-10-30 22:18                 ` Rob Herring
2019-10-31 10:09                   ` Lorenzo Pieralisi
2019-10-29 22:12     ` Bjorn Helgaas
2019-10-28 16:32 ` [PATCH v3 20/25] PCI: ftpci100: Use inbound resources for setup Rob Herring
2019-10-28 16:32 ` [PATCH v3 21/25] PCI: v3-semi: " Rob Herring
2019-10-28 16:32 ` [PATCH v3 22/25] PCI: xgene: " Rob Herring
2019-10-28 16:32 ` [PATCH v3 23/25] PCI: iproc: " Rob Herring
2019-10-29 15:59   ` Srinath Mannam
2019-10-28 16:32 ` [PATCH v3 24/25] PCI: rcar: " Rob Herring
2019-10-28 16:32 ` [PATCH v3 25/25] PCI: Make devm_of_pci_get_host_bridge_resources() static Rob Herring
2019-10-31 10:57 ` [PATCH v3 00/25] PCI host resource consolidation Lorenzo Pieralisi

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=CAFqH_53nX74vD6-T2ao0x540wq_NbN671H5i2fwbo6NaCgc4KQ@mail.gmail.com \
    --to=eballetbo@gmail.com \
    --cc=Zhiqiang.Hou@nxp.com \
    --cc=andrew.murray@arm.com \
    --cc=bcm-kernel-feedback-list@broadcom.com \
    --cc=bhelgaas@google.com \
    --cc=gustavo.pimentel@synopsys.com \
    --cc=hch@infradead.org \
    --cc=heiko@sntech.de \
    --cc=horms@verge.net.au \
    --cc=jingoohan1@gmail.com \
    --cc=lftan@altera.com \
    --cc=linus.walleij@linaro.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-mediatek@lists.infradead.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=linux-renesas-soc@vger.kernel.org \
    --cc=linux-rockchip@lists.infradead.org \
    --cc=lorenzo.pieralisi@arm.com \
    --cc=m.karthikeyan@mobiveil.co.in \
    --cc=matthias.bgg@gmail.com \
    --cc=michal.simek@xilinx.com \
    --cc=rfi@lists.rocketboards.org \
    --cc=rjui@broadcom.com \
    --cc=robh@kernel.org \
    --cc=ryder.lee@mediatek.com \
    --cc=sbranden@broadcom.com \
    --cc=shawn.lin@rock-chips.com \
    --cc=srinath.mannam@broadcom.com \
    --cc=thomas.petazzoni@bootlin.com \
    --cc=tjoseph@cadence.com \
    --cc=toan@os.amperecomputing.com \
    --cc=will@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).