From: Chen-Yu Tsai <wenst@chromium.org>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Cc: matthias.bgg@gmail.com, mturquette@baylibre.com,
sboyd@kernel.org, miles.chen@mediatek.com,
rex-bc.chen@mediatek.com, nfraprado@collabora.com,
chun-jie.chen@mediatek.com, jose.exposito89@gmail.com,
drinkcat@chromium.org, weiyi.lu@mediatek.com,
devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org
Subject: Re: [PATCH 08/10] clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents
Date: Wed, 7 Sep 2022 11:49:55 +0800 [thread overview]
Message-ID: <CAGXv+5G52--wF=e=nd3ezDPoQcOdsqMd_1WdzGEWxjjZaJsRLg@mail.gmail.com> (raw)
In-Reply-To: <20220905100416.42421-9-angelogioacchino.delregno@collabora.com>
Hi,
On Mon, Sep 5, 2022 at 6:04 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> These PLLs are conflicting with GPU rates that can be generated by
> the GPU-dedicated MFGPLL and would require a special clock handler
> to be used, for very little and ignorable power consumption benefits.
> Also, we're in any case unable to set the rate of these PLLs to
> something else that is sensible for this task, so simply drop them:
> this will make the GPU to be clocked exclusively from MFGPLL for
> "fast" rates, while still achieving the right "safe" rate during
> PLL frequency locking.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/clk/mediatek/clk-mt8195-topckgen.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-mt8195-topckgen.c b/drivers/clk/mediatek/clk-mt8195-topckgen.c
> index 4dde23bece66..6ff610c101ae 100644
> --- a/drivers/clk/mediatek/clk-mt8195-topckgen.c
> +++ b/drivers/clk/mediatek/clk-mt8195-topckgen.c
> @@ -301,8 +301,6 @@ static const char * const ipu_if_parents[] = {
> static const char * const mfg_parents[] = {
> "clk26m",
> "mainpll_d5_d2",
> - "univpll_d6",
> - "univpll_d7"
I'd just comment them out and leave a note about it. Or remove them but
leave a note. Removed code will not be obvious to others. And given this
is probably the only public documentation of the hardware, it'd be a shame
to lose evidence of it.
ChenYu
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next prev parent reply other threads:[~2022-09-07 3:52 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-05 10:04 [PATCH 00/10] MediaTek SoC safe clock muxing and GPU clocks AngeloGioacchino Del Regno
2022-09-05 10:04 ` [PATCH 01/10] arm64: dts: mt8183: Fix Mali GPU clock AngeloGioacchino Del Regno
2022-09-05 10:04 ` [PATCH 02/10] clk: mediatek: mt8183: mfgcfg: Propagate rate changes to parent AngeloGioacchino Del Regno
2022-09-05 10:04 ` [PATCH 03/10] clk: mediatek: mux: add clk notifier functions AngeloGioacchino Del Regno
2022-09-07 22:59 ` Miles Chen
2022-09-05 10:04 ` [PATCH 04/10] clk: mediatek: mt8183: Add clk mux notifier for MFG mux AngeloGioacchino Del Regno
2022-09-07 23:04 ` Miles Chen
2022-09-05 10:04 ` [PATCH 05/10] clk: mediatek: clk-mt8195-mfg: Reparent mfg_bg3d and propagate rate changes AngeloGioacchino Del Regno
2022-09-05 10:04 ` [PATCH 06/10] clk: mediatek: clk-mt8195-topckgen: Register mfg_ck_fast_ref as generic mux AngeloGioacchino Del Regno
2022-09-05 10:04 ` [PATCH 07/10] clk: mediatek: clk-mt8195-topckgen: Add GPU clock mux notifier AngeloGioacchino Del Regno
2022-09-07 23:05 ` Miles Chen
2022-09-05 10:04 ` [PATCH 08/10] clk: mediatek: clk-mt8195-topckgen: Drop univplls from mfg mux parents AngeloGioacchino Del Regno
2022-09-07 3:49 ` Chen-Yu Tsai [this message]
2022-09-07 7:46 ` AngeloGioacchino Del Regno
2022-09-05 10:04 ` [PATCH 09/10] clk: mediatek: clk-mt8192-mfg: Propagate rate changes to parent AngeloGioacchino Del Regno
2022-09-05 10:04 ` [PATCH 10/10] clk: mediatek: clk-mt8192: Add clock mux notifier for mfg_pll_sel AngeloGioacchino Del Regno
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