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[209.85.208.174]) by smtp.gmail.com with ESMTPSA id d24sm829795lfc.225.2021.02.04.19.21.33 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 Feb 2021 19:21:33 -0800 (PST) Received: by mail-lj1-f174.google.com with SMTP id f2so6016492ljp.11 for ; Thu, 04 Feb 2021 19:21:33 -0800 (PST) X-Received: by 2002:a2e:9d04:: with SMTP id t4mr1458674lji.56.1612495293179; Thu, 04 Feb 2021 19:21:33 -0800 (PST) MIME-Version: 1.0 References: <20210204184710.1880895-1-jernej.skrabec@siol.net> <20210204184710.1880895-3-jernej.skrabec@siol.net> In-Reply-To: <20210204184710.1880895-3-jernej.skrabec@siol.net> From: Chen-Yu Tsai Date: Fri, 5 Feb 2021 11:21:22 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 2/5] drm/sun4i: tcon: set sync polarity for tcon1 channel To: Jernej Skrabec X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210204_222137_644607_2DF0F077 X-CRM114-Status: GOOD ( 24.26 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stephen Boyd , Mike Turquette , Andre Heider , linux-kernel , Maxime Ripard , David Airlie , linux-sunxi , dri-devel , Daniel Vetter , linux-clk , linux-arm-kernel Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Feb 5, 2021 at 2:48 AM Jernej Skrabec wrote: > > Channel 1 has polarity bits for vsync and hsync signals but driver never > sets them. It turns out that with pre-HDMI2 controllers seemingly there > is no issue if polarity is not set. However, with HDMI2 controllers > (H6) there often comes to de-synchronization due to phase shift. This > causes flickering screen. It's safe to assume that similar issues might > happen also with pre-HDMI2 controllers. > > Solve issue with setting vsync and hsync polarity. Note that display > stacks with tcon top have polarity bits actually in tcon0 polarity > register. > > Fixes: 9026e0d122ac ("drm: Add Allwinner A10 Display Engine support") > Tested-by: Andre Heider > Signed-off-by: Jernej Skrabec > --- > drivers/gpu/drm/sun4i/sun4i_tcon.c | 24 ++++++++++++++++++++++++ > drivers/gpu/drm/sun4i/sun4i_tcon.h | 5 +++++ > 2 files changed, 29 insertions(+) > > diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c > index 6b9af4c08cd6..0d132dae58c0 100644 > --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c > +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c > @@ -672,6 +672,29 @@ static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, > SUN4I_TCON1_BASIC5_V_SYNC(vsync) | > SUN4I_TCON1_BASIC5_H_SYNC(hsync)); > > + /* Setup the polarity of sync signals */ > + if (tcon->quirks->polarity_in_ch0) { > + val = 0; > + > + if (mode->flags & DRM_MODE_FLAG_PHSYNC) > + val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE; > + > + if (mode->flags & DRM_MODE_FLAG_PVSYNC) > + val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE; > + > + regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val); > + } else { > + val = SUN4I_TCON1_IO_POL_UNKNOWN; I think a comment for the origin of this is warranted. Otherwise, Reviewed-by: Chen-Yu Tsai > + > + if (mode->flags & DRM_MODE_FLAG_PHSYNC) > + val |= SUN4I_TCON1_IO_POL_HSYNC_POSITIVE; > + > + if (mode->flags & DRM_MODE_FLAG_PVSYNC) > + val |= SUN4I_TCON1_IO_POL_VSYNC_POSITIVE; > + > + regmap_write(tcon->regs, SUN4I_TCON1_IO_POL_REG, val); > + } > + > /* Map output pins to channel 1 */ > regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, > SUN4I_TCON_GCTL_IOMAP_MASK, > @@ -1500,6 +1523,7 @@ static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = { > > static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks = { > .has_channel_1 = true, > + .polarity_in_ch0 = true, > .set_mux = sun8i_r40_tcon_tv_set_mux, > }; > > diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h > index c5ac1b02482c..b504fb2d3de5 100644 > --- a/drivers/gpu/drm/sun4i/sun4i_tcon.h > +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h > @@ -154,6 +154,10 @@ > #define SUN4I_TCON1_BASIC5_V_SYNC(height) (((height) - 1) & 0x3ff) > > #define SUN4I_TCON1_IO_POL_REG 0xf0 > +#define SUN4I_TCON1_IO_POL_UNKNOWN BIT(26) > +#define SUN4I_TCON1_IO_POL_HSYNC_POSITIVE BIT(25) > +#define SUN4I_TCON1_IO_POL_VSYNC_POSITIVE BIT(24) > + > #define SUN4I_TCON1_IO_TRI_REG 0xf4 > > #define SUN4I_TCON_ECC_FIFO_REG 0xf8 > @@ -236,6 +240,7 @@ struct sun4i_tcon_quirks { > bool needs_de_be_mux; /* sun6i needs mux to select backend */ > bool needs_edp_reset; /* a80 edp reset needed for tcon0 access */ > bool supports_lvds; /* Does the TCON support an LVDS output? */ > + bool polarity_in_ch0; /* some tcon1 channels have polarity bits in tcon0 pol register */ > u8 dclk_min_div; /* minimum divider for TCON0 DCLK */ > > /* callback to handle tcon muxing options */ > -- > 2.30.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel