[PATCH 1/2] soc: imx: gpcv2: Add support for imx8mm

[PATCH 1/2] soc: imx: gpcv2: Add support for imx8mm

[Adam Ford]

The technical reference manual for both the i.MX8MQ and i.MX8M Mini
appear to show the same register definitions and locations for the
General Power Controller (GPC).

This patch expands the table of compatible SoC's to include
the i.MX8m Mini

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index b0dffb06c05d..67c54cbb6c81 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -641,6 +641,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
 static const struct of_device_id imx_gpcv2_dt_ids[] = {
 	{ .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
 	{ .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
+	{ .compatible = "fsl,imx8mm-gpc", .data = &imx8m_pgc_domain_data, },
 	{ }
 };
 
-- 
2.20.1


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[PATCH 2/2] arm64: dts: Add GPC Support

[Adam Ford]

The General Power Controller (GPC) used on the i.MX8MQ is the
same as what is used on the i.MX8M Mini.

This patch adds the GPC support to the device tree for the SoC.

Signed-off-by: Adam Ford <aford173@gmail.com>

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 6edbdfe2d0d7..860cddec9632 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -4,6 +4,7 @@
  */
 
 #include <dt-bindings/clock/imx8mm-clock.h>
+#include <dt-bindings/power/imx8mq-power.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -498,6 +499,90 @@
 				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 				#reset-cells = <1>;
 			};
+
+			gpc: gpc@303a0000 {
+				compatible = "fsl,imx8mm-gpc";
+				reg = <0x303a0000 0x10000>;
+				interrupt-parent = <&gic>;
+				interrupt-controller;
+				#interrupt-cells = <3>;
+
+				pgc {
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					pgc_mipi: power-domain@0 {
+						#power-domain-cells = <0>;
+						reg = <IMX8M_POWER_DOMAIN_MIPI>;
+					};
+
+					/*
+					 * As per comment in ATF source code:
+					 *
+					 * PCIE1 and PCIE2 share the
+					 * same reset signal, if we
+					 * power down PCIE2, PCIE1
+					 * will be held in reset too.
+					 *
+					 * So instead of creating two
+					 * separate power domains for
+					 * PCIE1 and PCIE2 we create a
+					 * link between both and use
+					 * it as a shared PCIE power
+					 * domain.
+					 */
+					pgc_pcie: power-domain@1 {
+						#power-domain-cells = <0>;
+						reg = <IMX8M_POWER_DOMAIN_PCIE1>;
+						power-domains = <&pgc_pcie2>;
+					};
+
+					pgc_otg1: power-domain@2 {
+						#power-domain-cells = <0>;
+						reg = <IMX8M_POWER_DOMAIN_USB_OTG1>;
+					};
+
+					pgc_otg2: power-domain@3 {
+						#power-domain-cells = <0>;
+						reg = <IMX8M_POWER_DOMAIN_USB_OTG2>;
+					};
+
+					pgc_ddr1: power-domain@4 {
+						#power-domain-cells = <0>;
+						reg = <IMX8M_POWER_DOMAIN_DDR1>;
+					};
+
+					pgc_gpu: power-domain@5 {
+						#power-domain-cells = <0>;
+						reg = <IMX8M_POWER_DOMAIN_GPU>;
+					};
+
+					pgc_vpu: power-domain@6 {
+						#power-domain-cells = <0>;
+						reg = <IMX8M_POWER_DOMAIN_VPU>;
+					};
+
+					pgc_disp: power-domain@7 {
+						#power-domain-cells = <0>;
+						reg = <IMX8M_POWER_DOMAIN_DISP>;
+					};
+
+					pgc_mipi_csi1: power-domain@8 {
+						#power-domain-cells = <0>;
+						reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>;
+					};
+
+					pgc_mipi_csi2: power-domain@9 {
+						#power-domain-cells = <0>;
+						reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>;
+					};
+
+					pgc_pcie2: power-domain@a {
+						#power-domain-cells = <0>;
+						reg = <IMX8M_POWER_DOMAIN_PCIE2>;
+					};
+				};
+			};
 		};
 
 		aips2: bus@30400000 {
-- 
2.20.1


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Re: [PATCH 2/2] arm64: dts: Add GPC Support

[Fabio Estevam]

Hi Adam,

On Fri, Nov 29, 2019 at 8:41 PM Adam Ford <aford173@gmail.com> wrote:

> +
> +                       gpc: gpc@303a0000 {
> +                               compatible = "fsl,imx8mm-gpc";

You could do like this instead:

compatible = "fsl,imx8mm-gpc", "fsl,imx8mq-gpc";

and then you don't need patch 1/2.

Also, "fsl,imx8mm-gpc" needs to be documented.

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Re: [PATCH 2/2] arm64: dts: Add GPC Support

[Fabio Estevam]

On Sat, Nov 30, 2019 at 7:25 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> Hi Adam,
>
> On Fri, Nov 29, 2019 at 8:41 PM Adam Ford <aford173@gmail.com> wrote:
>
> > +
> > +                       gpc: gpc@303a0000 {
> > +                               compatible = "fsl,imx8mm-gpc";
>
> You could do like this instead:
>
> compatible = "fsl,imx8mm-gpc", "fsl,imx8mq-gpc";
>
> and then you don't need patch 1/2.
>
> Also, "fsl,imx8mm-gpc" needs to be documented.

One more thing: when you add a v2, please specify the SoC name in the
subject line:

arm64: dts: imx8mm: Add GPC Support

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Re: [PATCH 2/2] arm64: dts: Add GPC Support

[Adam Ford]

On Sat, Nov 30, 2019 at 4:30 PM Fabio Estevam <festevam@gmail.com> wrote:
>
> On Sat, Nov 30, 2019 at 7:25 PM Fabio Estevam <festevam@gmail.com> wrote:
> >
> > Hi Adam,
> >
> > On Fri, Nov 29, 2019 at 8:41 PM Adam Ford <aford173@gmail.com> wrote:
> >
> > > +
> > > +                       gpc: gpc@303a0000 {
> > > +                               compatible = "fsl,imx8mm-gpc";
> >
> > You could do like this instead:
> >
> > compatible = "fsl,imx8mm-gpc", "fsl,imx8mq-gpc";
> >
> > and then you don't need patch 1/2.

I like that idea.

> >
> > Also, "fsl,imx8mm-gpc" needs to be documented.

I held off intentionally because of all the txt->yaml conversion, I
didn't want to get stuck in the middle of that.

Would an tweak to the txt file be accepted?

If not, should I just use the "fsl,imx8mq-gpc" and leave it alone?

>
> One more thing: when you add a v2, please specify the SoC name in the
> subject line:
>
> arm64: dts: imx8mm: Add GPC Support

Good catch.  Sorry about that.


adam

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Re: [PATCH 2/2] arm64: dts: Add GPC Support

[Fabio Estevam]

On Sat, Nov 30, 2019 at 7:50 PM Adam Ford <aford173@gmail.com> wrote:

> I held off intentionally because of all the txt->yaml conversion, I
> didn't want to get stuck in the middle of that.
>
> Would an tweak to the txt file be accepted?

Yes, a patch to the existing txt binding should be fine.

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Re: [PATCH 1/2] soc: imx: gpcv2: Add support for imx8mm

[Philipp Zabel]

On Fri, 2019-11-29 at 17:41 -0600, Adam Ford wrote:
> The technical reference manual for both the i.MX8MQ and i.MX8M Mini
> appear to show the same register definitions and locations for the
> General Power Controller (GPC).
> 
> This patch expands the table of compatible SoC's to include
> the i.MX8m Mini
> 
> Signed-off-by: Adam Ford <aford173@gmail.com>
> 
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
> index b0dffb06c05d..67c54cbb6c81 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -641,6 +641,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
>  static const struct of_device_id imx_gpcv2_dt_ids[] = {
>  	{ .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
>  	{ .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
> +	{ .compatible = "fsl,imx8mm-gpc", .data = &imx8m_pgc_domain_data, },

According to the 5.2.5.1 "PGC power domains" chapters in both the i.MX
8M Dual/8M QuadLite/8M Quad and i.MX 8M Mini Applications Processor
Reference Manuals (Rev.1), the two SoCs have a different list of power
domains:

i.MX8MQ:
	PGC_C0
	PGC_C1
	PGC_C2
	PGC_C3
	PGC_SCU
	PGC_MF
	PGC_OTG1
	PGC_OTG2
	PGC_PCIE
	PGC_MIPI
	PGC_DDR1
	PGC_DDR2
	PGC_VPU
	PGC_GPU
	PGC_HDMI
	PGC_DISP
	PGC_MIPI_CSI1
	PGC_MIPI_CSI2
	PGC_PCIE2

i.MX8MM:
	PGC_C0
	PGC_C1
	PGC_C2
	PGC_C3
	PGC_SCU
	PGC_NOC
	PGC_PCIE
	PGC_OTG1
	PGC_OTG2
	PGC_DDR1
	PGC_DISPMIX
	GPC_MIPI
	PGC_GPUMIX
	PGC_GPU_3D
	PGC_GPU_2D
	PGC_VPUMIX
	PGC_VPU_G1
	PGC_VPU_G2
	PGC_VPU_H1

regards
Philipp


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Re: [PATCH 1/2] soc: imx: gpcv2: Add support for imx8mm

[Adam Ford]

On Mon, Dec 2, 2019 at 8:28 AM Philipp Zabel <p.zabel@pengutronix.de> wrote:
>
> On Fri, 2019-11-29 at 17:41 -0600, Adam Ford wrote:
> > The technical reference manual for both the i.MX8MQ and i.MX8M Mini
> > appear to show the same register definitions and locations for the
> > General Power Controller (GPC).
> >
> > This patch expands the table of compatible SoC's to include
> > the i.MX8m Mini
> >
> > Signed-off-by: Adam Ford <aford173@gmail.com>
> >
> > diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
> > index b0dffb06c05d..67c54cbb6c81 100644
> > --- a/drivers/soc/imx/gpcv2.c
> > +++ b/drivers/soc/imx/gpcv2.c
> > @@ -641,6 +641,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
> >  static const struct of_device_id imx_gpcv2_dt_ids[] = {
> >       { .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
> >       { .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
> > +     { .compatible = "fsl,imx8mm-gpc", .data = &imx8m_pgc_domain_data, },
>
> According to the 5.2.5.1 "PGC power domains" chapters in both the i.MX
> 8M Dual/8M QuadLite/8M Quad and i.MX 8M Mini Applications Processor
> Reference Manuals (Rev.1), the two SoCs have a different list of power
> domains:

Shoot.  I needed to go further down in the table.  I stopped after the
first four.

Sorry for the noise.

adam
>
> i.MX8MQ:
>         PGC_C0
>         PGC_C1
>         PGC_C2
>         PGC_C3
>         PGC_SCU
>         PGC_MF
>         PGC_OTG1
>         PGC_OTG2
>         PGC_PCIE
>         PGC_MIPI
>         PGC_DDR1
>         PGC_DDR2
>         PGC_VPU
>         PGC_GPU
>         PGC_HDMI
>         PGC_DISP
>         PGC_MIPI_CSI1
>         PGC_MIPI_CSI2
>         PGC_PCIE2
>
> i.MX8MM:
>         PGC_C0
>         PGC_C1
>         PGC_C2
>         PGC_C3
>         PGC_SCU
>         PGC_NOC
>         PGC_PCIE
>         PGC_OTG1
>         PGC_OTG2
>         PGC_DDR1
>         PGC_DISPMIX
>         GPC_MIPI
>         PGC_GPUMIX
>         PGC_GPU_3D
>         PGC_GPU_2D
>         PGC_VPUMIX
>         PGC_VPU_G1
>         PGC_VPU_G2
>         PGC_VPU_H1
>
> regards
> Philipp
>

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Re: [PATCH 1/2] soc: imx: gpcv2: Add support for imx8mm

[Adam Ford]

On Mon, Dec 2, 2019 at 9:17 AM Adam Ford <aford173@gmail.com> wrote:
>
> On Mon, Dec 2, 2019 at 8:28 AM Philipp Zabel <p.zabel@pengutronix.de> wrote:
> >
> > On Fri, 2019-11-29 at 17:41 -0600, Adam Ford wrote:
> > > The technical reference manual for both the i.MX8MQ and i.MX8M Mini
> > > appear to show the same register definitions and locations for the
> > > General Power Controller (GPC).
> > >
> > > This patch expands the table of compatible SoC's to include
> > > the i.MX8m Mini
> > >
> > > Signed-off-by: Adam Ford <aford173@gmail.com>
> > >
> > > diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
> > > index b0dffb06c05d..67c54cbb6c81 100644
> > > --- a/drivers/soc/imx/gpcv2.c
> > > +++ b/drivers/soc/imx/gpcv2.c
> > > @@ -641,6 +641,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
> > >  static const struct of_device_id imx_gpcv2_dt_ids[] = {
> > >       { .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
> > >       { .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
> > > +     { .compatible = "fsl,imx8mm-gpc", .data = &imx8m_pgc_domain_data, },
> >
> > According to the 5.2.5.1 "PGC power domains" chapters in both the i.MX
> > 8M Dual/8M QuadLite/8M Quad and i.MX 8M Mini Applications Processor
> > Reference Manuals (Rev.1), the two SoCs have a different list of power
> > domains:
>
> Shoot.  I needed to go further down in the table.  I stopped after the
> first four.
>
> Sorry for the noise.
>
> adam
> >
> > i.MX8MQ:
> >         PGC_C0
> >         PGC_C1
> >         PGC_C2
> >         PGC_C3
> >         PGC_SCU
> >         PGC_MF
> >         PGC_OTG1
> >         PGC_OTG2
> >         PGC_PCIE
> >         PGC_MIPI
> >         PGC_DDR1
> >         PGC_DDR2
> >         PGC_VPU
> >         PGC_GPU
> >         PGC_HDMI
> >         PGC_DISP
> >         PGC_MIPI_CSI1
> >         PGC_MIPI_CSI2
> >         PGC_PCIE2
> >
> > i.MX8MM:
> >         PGC_C0
> >         PGC_C1
> >         PGC_C2
> >         PGC_C3
> >         PGC_SCU
> >         PGC_NOC
> >         PGC_PCIE
> >         PGC_OTG1
> >         PGC_OTG2
> >         PGC_DDR1
> >         PGC_DISPMIX
> >         GPC_MIPI
> >         PGC_GPUMIX
> >         PGC_GPU_3D
> >         PGC_GPU_2D
> >         PGC_VPUMIX
> >         PGC_VPU_G1
> >         PGC_VPU_G2
> >         PGC_VPU_H1
Philipp,

Thanks for reviewing it and catching my mistake.

I went though the datasheet more thoroughly, and I think I have the
table correct for the i.MX8M Mini.  With that and a small tweak to the
OTG nodes, I was able to use USB OTG1 and OTG2 ports.

I am going to submit a V2 fix tomorrow after I clean it up.  I'll do a
multi-part series where part 1 is the GPC, part 2 will be the OTG
updates, and if I get more peripherals working, I'll add them as
additional parts to the series.

adam
> >
> > regards
> > Philipp
> >

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