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bh=mwxXyZxIZHGZE+VqrQfLFIHJrRDm5TdpZ7b2DJmK44k=; b=V3yBBZppNtITcNoB20FH5g+fvyydGAWnz9MY4QefFG016ai7nWsQsefFZzakgtXdYp oYkhp7Ns/V6teI6OozLVSu0WS/EEgTyBfh61NsS1JlD3M8nRuYXbggFLl4eyK9+LSYjc kTTTy06KHXM3N9EKfFQqsG0q0cW8mYQ4VyY3BkFVLury+5a4FOiGzPWCe4Nbi1Xx3M3g XPK85mwWRLkQ0KPX12eY1LVwuhSbIJTK+kckxYDpzcxaQM4XwHUBrIbOK2kx7MfssO/L YlPfRVcgnVurvZzd2Cr+way7qL+J0j8RJO+E7ZVZiERlKxpNlbHJMKUyXPOlAbFDyTAl Gd5A== X-Gm-Message-State: AOAM532wYrnej6tZ618K4EKSpeyfMoAMOVomLoAsct8ZavkRmHFJWRCk cjqrBK5lQqq0WjoDqOdZhL+UIz7BzOiJ1PTNnSz0Dw== X-Google-Smtp-Source: ABdhPJw54oMIdnl9vOHiG1OEJIWO1gTLhLL8nSGyz80aFrNrjsxp0x9bxGNEs/AhBARq9eWQ7ZOaUQFwJ++I1qvwNAQ= X-Received: by 2002:a2e:9a46:: with SMTP id k6mr6565907ljj.310.1603725209206; Mon, 26 Oct 2020 08:13:29 -0700 (PDT) MIME-Version: 1.0 References: <20201011182254.17776-7-rayagonda.kokatanur@broadcom.com> In-Reply-To: From: Rayagonda Kokatanur Date: Mon, 26 Oct 2020 20:43:17 +0530 Message-ID: Subject: Re: [PATCH v1 6/6] i2c: iproc: handle rx fifo full interrupt To: Dhananjay Phadke X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201026_111331_614878_5A4995F8 X-CRM114-Status: GOOD ( 16.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Lori Hikichi , Florian Fainelli , Scott Branden , Ray Jui , Brendan Higgins , Linux Kernel Mailing List , Wolfram Sang , BCM Kernel Feedback , linux-i2c , Ray Jui , Andy Shevchenko , linux-arm Mailing List Content-Type: multipart/mixed; boundary="===============4163149979085425650==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============4163149979085425650== Content-Type: multipart/signed; protocol="application/pkcs7-signature"; micalg=sha-256; boundary="000000000000735da305b2945fa2" --000000000000735da305b2945fa2 Content-Type: text/plain; charset="UTF-8" Hi Dhanajay, On Fri, Oct 23, 2020 at 11:12 PM Ray Jui wrote: > > > > On 10/12/2020 3:03 PM, Dhananjay Phadke wrote: > > From: Rayagonda Kokatanur > > > > On Sun, 11 Oct 2020 23:52:54 +0530, Rayagonda Kokatanur wrote: > >> Add code to handle IS_S_RX_FIFO_FULL_SHIFT interrupt to support > >> master write request with >= 64 bytes. > >> > >> Iproc has a slave rx fifo size of 64 bytes. > >> Rx fifo full interrupt (IS_S_RX_FIFO_FULL_SHIFT) will be generated > >> when RX fifo becomes full. This can happen if master issues write > >> request of more than 64 bytes. > >> > > > > ARM cores run much faster than I2C bus, why would rx fifo go full when > > rx interrupt is enabled and bytes are read out by bus driver isr? > > Isn't fifo read pointer updated on these byte reads? > > Hi Rayagonda, > > Could you please reply on this question? For transactions > 64 bytes, do > we batch until RX FIFO is full before we read out the data? Sorry I missed this question. Yes with current design we are batching 64 bytes for translation > 64 bytes. Best regards, Rayagonda > > Thanks, > > Ray > > > Does controller stretch clock when rx fifo is full (e.g. kernel has > > crashed, bus driver isn't draining fifo)? > > --000000000000735da305b2945fa2 Content-Type: application/pkcs7-signature; name="smime.p7s" Content-Transfer-Encoding: base64 Content-Disposition: attachment; filename="smime.p7s" Content-Description: S/MIME Cryptographic Signature MIIQVwYJKoZIhvcNAQcCoIIQSDCCEEQCAQExDzANBglghkgBZQMEAgEFADALBgkqhkiG9w0BBwGg gg2sMIIE6DCCA9CgAwIBAgIOSBtqCRO9gCTKXSLwFPMwDQYJKoZIhvcNAQELBQAwTDEgMB4GA1UE CxMXR2xvYmFsU2lnbiBSb290IENBIC0gUjMxEzARBgNVBAoTCkdsb2JhbFNpZ24xEzARBgNVBAMT Ckdsb2JhbFNpZ24wHhcNMTYwNjE1MDAwMDAwWhcNMjQwNjE1MDAwMDAwWjBdMQswCQYDVQQGEwJC RTEZMBcGA1UEChMQR2xvYmFsU2lnbiBudi1zYTEzMDEGA1UEAxMqR2xvYmFsU2lnbiBQZXJzb25h bFNpZ24gMiBDQSAtIFNIQTI1NiAtIEczMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEA tpZok2X9LAHsYqMNVL+Ly6RDkaKar7GD8rVtb9nw6tzPFnvXGeOEA4X5xh9wjx9sScVpGR5wkTg1 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