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h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=0mLqGazU6rN+in+HWOWWGDjbKCiAOq44ih/Rglku8rg=; b=VwuFppSkhDqnW+IHf6cvqnM2ui1qL/AMsyj5NMgI4YnEWXa8BdfYbP1QE/AnNLcQqz rluqkqRpQU6ZMW4ZKLaJBvjwj1Q+v3EaW3nERMgk1AC1GEAs51LrMZOJh3KbFFCLEBDC rNqCHN7QnKmmoPzWCLYkf/G+OxJ9fPqa1Uj0UIS3ryuj5S+LXoE6MOwCWpXYu5e/qcHk jRleVNRVYLRU0/1g/qwPwbSSYFAALgwespq0MYskXAVPG5bYL7Fjrg42xJaIuiBN0Bge r3YtYlLViwOoYN+Q7VsGaKvVklI7exWvSji3jXcijGmMveIQfYS6L0VTGV8blp0zpsMj r4sg== X-Gm-Message-State: APjAAAWGjhKd7QRbEXLfcQAcDIa2umV4FsEnfjrcYDCUmh9risg178+z TbSUHyY6DS5WtrljAF9EMQ8uyPjSEw8lgcbKsphz5aty X-Google-Smtp-Source: APXvYqzkXYaFtSVz0r3/YbiSI3rEnLnbNBPwbLaqqDPdL/bqp2Odb2cFHlPB+wPNyZkdSZDrf6+B1sgMlUrF1SiEbbk= X-Received: by 2002:a2e:8905:: with SMTP id d5mr919358lji.59.1554193508040; Tue, 02 Apr 2019 01:25:08 -0700 (PDT) MIME-Version: 1.0 References: <20190214175725.60462-1-ray.jui@broadcom.com> <20190214175725.60462-3-ray.jui@broadcom.com> <20190327221452.GA15396@kunai> In-Reply-To: From: Rayagonda Kokatanur Date: Tue, 2 Apr 2019 13:54:56 +0530 Message-ID: Subject: Re: [PATCH v5 2/8] i2c: iproc: Add slave mode support To: Ray Jui X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190402_012510_950200_AE6EA763 X-CRM114-Status: GOOD ( 21.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , devicetree@vger.kernel.org, Wolfram Sang , linux-kernel@vger.kernel.org, Shreesha Rajashekar , Rob Herring , bcm-kernel-feedback-list@broadcom.com, linux-i2c@vger.kernel.org, Michael Cheng , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Ray/Wolfram, On Tue, Apr 2, 2019 at 3:03 AM Ray Jui wrote: > > Hi Wolfram/Rayagonda, > > On 3/27/2019 3:14 PM, Wolfram Sang wrote: > > > >> +static void bcm_iproc_i2c_slave_init( > >> + struct bcm_iproc_i2c_dev *iproc_i2c, bool need_reset) > >> +{ > >> + u32 val; > >> + > >> + if (need_reset) { > >> + /* put controller in reset */ > >> + val = readl(iproc_i2c->base + CFG_OFFSET); > >> + val |= BIT(CFG_RESET_SHIFT); > >> + writel(val, iproc_i2c->base + CFG_OFFSET); > >> + > >> + /* wait 100 usec per spec */ > >> + udelay(100); > >> + > >> + /* bring controller out of reset */ > >> + val &= ~(BIT(CFG_RESET_SHIFT)); > >> + writel(val, iproc_i2c->base + CFG_OFFSET); > >> + } > >> + > >> + /* flush TX/RX FIFOs */ > >> + val = (BIT(S_FIFO_RX_FLUSH_SHIFT) | BIT(S_FIFO_TX_FLUSH_SHIFT)); > >> + writel(val, iproc_i2c->base + S_FIFO_CTRL_OFFSET); > > > > Will flushing FIFOs work when a slave is register while a master > > transfer is on-going at the same time? > > > > Okay, as you pointed out in a subsequent email, this can't happen. > > >> + > >> + /* RANDOM SLAVE STRETCH time - 20ms*/ > > > > What is a "random stretch time"? 20ms sounds like a lot. Also, missing > > space before comment terminator. > > > > Rayagonda, > > Could you please help to comment on the choice of the 20 ms to allow > clock stretch from the slave? In probably all cases, the slave should > not need more than 1 ms? 20 ms does seem way too long as Wolfram pointed > out. In fact we are programming max slave stretch time ie 25ms, comment should be correcting. Its maximum time for slave to complete read/write operation, if slave is done with read/write then clock will not be stretched further, it will be released immediately. Hence I feel no harm in programming max timeout value. Also determining correct slave stretch is very subjective and depends on slave type as well. Best regards, Rayagonda > > Will fix the missing space before comment terminator. > > >> @@ -224,22 +473,25 @@ static int bcm_iproc_i2c_init(struct bcm_iproc_i2c_dev *iproc_i2c) > >> > >> /* put controller in reset */ > >> val = readl(iproc_i2c->base + CFG_OFFSET); > >> - val |= 1 << CFG_RESET_SHIFT; > >> - val &= ~(1 << CFG_EN_SHIFT); > >> + val |= BIT(CFG_RESET_SHIFT); > >> + val &= ~(BIT(CFG_EN_SHIFT)); > >> writel(val, iproc_i2c->base + CFG_OFFSET); > >> > >> /* wait 100 usec per spec */ > >> udelay(100); > >> > >> /* bring controller out of reset */ > >> - val &= ~(1 << CFG_RESET_SHIFT); > >> + val &= ~(BIT(CFG_RESET_SHIFT)); > >> writel(val, iproc_i2c->base + CFG_OFFSET); > >> > >> /* flush TX/RX FIFOs and set RX FIFO threshold to zero */ > >> - val = (1 << M_FIFO_RX_FLUSH_SHIFT) | (1 << M_FIFO_TX_FLUSH_SHIFT); > >> + val = (BIT(M_FIFO_RX_FLUSH_SHIFT) | BIT(M_FIFO_TX_FLUSH_SHIFT)); > >> writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET); > >> /* disable all interrupts */ > >> - writel(0, iproc_i2c->base + IE_OFFSET); > >> + val = readl(iproc_i2c->base + IE_OFFSET); > >> + val &= ~(IE_M_ALL_INTERRUPT_MASK << > >> + IE_M_ALL_INTERRUPT_SHIFT); > >> + writel(val, iproc_i2c->base + IE_OFFSET); > > > > This block looks unrelated, but I won't be too strict here... > > > >> + case M_CMD_STATUS_FIFO_UNDERRUN: > >> + dev_dbg(iproc_i2c->device, "FIFO under-run\n"); > >> + return -ENXIO; > >> + > >> + case M_CMD_STATUS_RX_FIFO_FULL: > >> + dev_dbg(iproc_i2c->device, "Master Rx FIFO full > 10ms\n"); > >> + return -ETIMEDOUT; > >> + > > > > ... however, this looks really unrelated to me. This is about master > > transmission, or? > > This should be submitted in a separate commit. Will do that in the next > iteration of patch series. > > > > > Rest looks OK. > > > > Thanks, > > Ray _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel