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[209.85.167.42]) by smtp.gmail.com with ESMTPSA id n21sm664690lfb.81.2019.02.14.09.51.38 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 Feb 2019 09:51:38 -0800 (PST) Received: by mail-lf1-f42.google.com with SMTP id u21so5215756lfu.1 for ; Thu, 14 Feb 2019 09:51:38 -0800 (PST) X-Received: by 2002:a19:2794:: with SMTP id n142mr3048400lfn.77.1550166697920; Thu, 14 Feb 2019 09:51:37 -0800 (PST) MIME-Version: 1.0 References: <1550089932-6888-1-git-send-email-longman@redhat.com> <1550089932-6888-3-git-send-email-longman@redhat.com> <20190214103333.GH32494@hirez.programming.kicks-ass.net> <9e01d4ef-56df-7af8-a0f5-b49644e298bf@redhat.com> In-Reply-To: <9e01d4ef-56df-7af8-a0f5-b49644e298bf@redhat.com> From: Linus Torvalds Date: Thu, 14 Feb 2019 09:51:21 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 2/2] locking/rwsem: Optimize down_read_trylock() To: Waiman Long X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190214_095143_915575_3BF3FF82 X-CRM114-Status: GOOD ( 13.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch , linux-xtensa@linux-xtensa.org, Davidlohr Bueso , linux-ia64@vger.kernel.org, Tim Chen , Arnd Bergmann , Linux-sh list , Peter Zijlstra , linux-hexagon@vger.kernel.org, the arch/x86 maintainers , Will Deacon , Linux List Kernel Mailing , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , "linux-alpha@vger.kernel.org" , sparclinux@vger.kernel.org, Thomas Gleixner , linuxppc-dev@lists.ozlabs.org, Andrew Morton , "linux-alpha@vger.kernel.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Feb 14, 2019 at 6:53 AM Waiman Long wrote: > > The ARM64 result is what I would have expected given that the change was > to optimize for the uncontended case. The x86-64 result is kind of an > anomaly to me, but I haven't bothered to dig into that. I would say that the ARM result is what I'd expect from something that scales badly to begin with. The x86-64 result is the expected one: yes, the cmpxchg is done one extra time, but it results in fewer cache transitions (the cacheline never goes into "shared" state), and cache transitions are what matter. The cost of re-doing the instruction should be low. The cacheline ping-pong and the cache coherency messages is what hurts. So I actually think both are very easily explained. The x86-64 number improves, because there is less cache coherency traffic. The arm64 numbers scaled horribly even before, and that's because there is too much ping-pong, and it's probably because there is no "stickiness" to the cacheline to the core, and thus adding the extra loop can make the ping-pong issue even worse because now there is more of it. The cachelines not sticking at all to a core probably is good for fairness issues (in particular, sticking *too* much can cause horrible issues), but it's absolutely horrible if it means that you lose the cacheline even before you get to complete the second cmpxchg. Linus _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel