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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=vHJ8DsHd+e4Pqmm9UcPGmKD9k74sR8ChOXKicy8wYjc=; b=IEDmdGDFch7ho+0FoRv56dVi75JLnvrCdVGjXwShyS/6wZkseNVHbM2YPkJ5Y1ARaz cVgiWbm2okx5p5O2KS/sZqX24D6F8uAyCnatV/W5qosddaWmgrZN2FiqxK2gJ521gQWj iMqZtqGeuFA27JVDhRIOKv0e2cF3YZtyaMV2jDS6FY5sxxg9XOgdNUD6LSfasOBQK7F7 pFIKLLOYuNt5YcrilxhJadSlmreEKe0Yt9nMW3+4k1s3SbkuSlcXSYI47NpCoGSZLjJR pRE7yDY5mjuF3mayzadWqg4HWRfqUA79c02wE4TQqwJvOYzvIlPxYIiHc7aeFStQv0/W mg2w== X-Gm-Message-State: AOAM530FmhaM4ppjnWcoHu8DOPDjnQlKfVcnSIW/lwsQ4u3ssTPrpIVe LOidm+UwoUvgB8Vm3uACD2DLw20NvuLwMAKYJmsXew== X-Google-Smtp-Source: ABdhPJys6sJzFV3QdVk29hjLhy6uoQDZeFGopmtFPLFKx3BnPKuHnD/3zxX2591Jy3sx3Ax4WzsnXeAVAROPyyN8lS4= X-Received: by 2002:a50:cc9a:: with SMTP id q26mr40569781edi.64.1600443290663; Fri, 18 Sep 2020 08:34:50 -0700 (PDT) MIME-Version: 1.0 References: <20200911084119.1080694-1-suzuki.poulose@arm.com> <20200911084119.1080694-9-suzuki.poulose@arm.com> In-Reply-To: <20200911084119.1080694-9-suzuki.poulose@arm.com> From: Mike Leach Date: Fri, 18 Sep 2020 16:34:40 +0100 Message-ID: Subject: Re: [PATCH 08/19] coresight: etm4x: Add commentary on the registers To: Suzuki K Poulose X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200918_113451_836576_EEBEBE1F X-CRM114-Status: GOOD ( 16.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Coresight ML , Anshuman.Khandual@arm.com, Mathieu Poirier , linux-arm-kernel , Leo Yan Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Reviewed-by: Mike Leach On Fri, 11 Sep 2020 at 09:41, Suzuki K Poulose wrote: > > As we are about define a switch..case table for individual register > access by offset for implementing the system instruction support, > document the possible set of registers for each group to make > it easier to co-relate. > > Cc: Mathieu Poirier > Cc: Mike Leach > Signed-off-by: Suzuki K Poulose > --- > drivers/hwtracing/coresight/coresight-etm4x.h | 21 ++++++++++++------- > 1 file changed, 13 insertions(+), 8 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 2746d3b591ca..c56ffec5d87e 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -44,13 +44,13 @@ > #define TRCVDSACCTLR 0x0A4 > #define TRCVDARCCTLR 0x0A8 > /* Derived resources registers */ > -#define TRCSEQEVRn(n) (0x100 + (n * 4)) > +#define TRCSEQEVRn(n) (0x100 + (n * 4)) /* n = 0-2 */ > #define TRCSEQRSTEVR 0x118 > #define TRCSEQSTR 0x11C > #define TRCEXTINSELR 0x120 > -#define TRCCNTRLDVRn(n) (0x140 + (n * 4)) > -#define TRCCNTCTLRn(n) (0x150 + (n * 4)) > -#define TRCCNTVRn(n) (0x160 + (n * 4)) > +#define TRCCNTRLDVRn(n) (0x140 + (n * 4)) /* n = 0-3 */ > +#define TRCCNTCTLRn(n) (0x150 + (n * 4)) /* n = 0-3 */ > +#define TRCCNTVRn(n) (0x160 + (n * 4)) /* n = 0-3 */ > /* ID registers */ > #define TRCIDR8 0x180 > #define TRCIDR9 0x184 > @@ -59,7 +59,7 @@ > #define TRCIDR12 0x190 > #define TRCIDR13 0x194 > #define TRCIMSPEC0 0x1C0 > -#define TRCIMSPECn(n) (0x1C0 + (n * 4)) > +#define TRCIMSPECn(n) (0x1C0 + (n * 4)) /* n = 1-7 */ > #define TRCIDR0 0x1E0 > #define TRCIDR1 0x1E4 > #define TRCIDR2 0x1E8 > @@ -68,9 +68,12 @@ > #define TRCIDR5 0x1F4 > #define TRCIDR6 0x1F8 > #define TRCIDR7 0x1FC > -/* Resource selection registers */ > +/* > + * Resource selection registers, n = 2-31. > + * First pair (regs 0, 1) is always present and is reserved. > + */ > #define TRCRSCTLRn(n) (0x200 + (n * 4)) > -/* Single-shot comparator registers */ > +/* Single-shot comparator registers, n = 0-7 */ > #define TRCSSCCRn(n) (0x280 + (n * 4)) > #define TRCSSCSRn(n) (0x2A0 + (n * 4)) > #define TRCSSPCICRn(n) (0x2C0 + (n * 4)) > @@ -80,11 +83,13 @@ > #define TRCPDCR 0x310 > #define TRCPDSR 0x314 > /* Trace registers (0x318-0xEFC) */ > -/* Comparator registers */ > +/* Address Comparator registers n = 0-15 */ > #define TRCACVRn(n) (0x400 + (n * 8)) > #define TRCACATRn(n) (0x480 + (n * 8)) > +/* Data Value Comparator Value registers, n = 0-7 */ > #define TRCDVCVRn(n) (0x500 + (n * 16)) > #define TRCDVCMRn(n) (0x580 + (n * 16)) > +/* ContextID/Virtual ContextID comparators, n = 0-7 */ > #define TRCCIDCVRn(n) (0x600 + (n * 8)) > #define TRCVMIDCVRn(n) (0x640 + (n * 8)) > #define TRCCIDCCTLR0 0x680 > -- > 2.24.1 > -- Mike Leach Principal Engineer, ARM Ltd. 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